Toshiba Memory Corporation

Kioxia Corporation

Masayoshi Sato

Kenichiro Suzuki

Ichirou Hara

According to one embodiment, a controller configured to manage second test information including status information indicating that a test related to a write operation and a read operation on a second storage area has not been executed. In response to receiving a command for acquiring information related to the second storage area from a host, the controller transmits the second test information to the host. When execution of the test on the second storage area is requested by the host, the controller executes the test related to the write operation and the read operation on the second storage area, and updates the status information of the second test information.

Memory system and information processing system for testing storage areas of nonvolatile memory

An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

Information processing system, storage device, and calibration method

According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Memory system

An information processing apparatus communicates with a storage device and includes a serial interface configured to support plural link rates, and a controller. The controller retrieves from the storage device via the serial interface information indicating a relationship between maximum power consumption and power consumption efficiency value for each link rate in a first power throttling mode that gives priority to performance and a second power throttling mode that gives priority to reduction of peak power, the power consumption efficiency value being a value that corresponds to the number of I/Os per watt, select the first or the second power throttling mode based on the retrieved information and a mode specified from one of three modes, and instruct the storage device to limit power consumption based on the selected power throttling mode. The three modes include a first mode that gives priority to performance, a second mode that gives priority to reduction of power consumption, and a third mode that gives priority to reduction of peak power.

Information processing apparatus, storage device, and method performed by host system

A storage device includes a receiving circuit including a correction circuit configured to correct an input signal from a host system based on correction factors and output the corrected input signal as an output signal containing a data value that is to be stored in the storage device, an interface controller configured to adjust the correction factors based on a difference value generated by the correction circuit using the output signal, and a transmission circuit configured to transmit the correction factors to the host system.

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Yokohama Kanagawa, Japan

Masayoshi Sato