Hitachi, Ltd.

Other

Hiatchi, Ltd.

Masayoshi Saito

Takuya Fukuda

Isamu Asano

Yoshitaka Nakamura

Makoto Yoshida

Naoki Yamamoto

Yoshikazu Tanabe

Nobuyoshi Natsuaki

Nobuyoshi Kobayashi

Masayoshi Hirasawa

Satoru Yamada

Hideo Aoki

Tsuyoshi Tamaru

Masayuki Suzuki

Yoshitaka Tadaki

Yoshifumi Kawamoto

Toshihiro Sekiguchi

Shinichi Fukada

Keizo Kawakita

Naoki Fukuda

Hidekazu Goto

Hiroyuki Uchiyama

Katsuhiko Hotta

Masayuki Kojima

Hiroyuki Maruyama

Susumu Takahashi

Tomonori Tanoue

Fumio Murai

Hiroshi Kawakami

Katsuhiko Mitani

Chushirou Kusano

Tadashi Umezawa

Hiroshi Miyazaki

With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor waferA having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor waferA heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor waferA, whereby the profile of the side-wall end portions of the gate electrode is improved

Fabrication process of a semiconductor integrated circuit device

With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor waferA having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor waferA heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor waferA, whereby the profile of the side-wall end portions of the gate electrode is improved.

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode ( ; see FIGS. and ) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film ( ) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen

With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer A, whereby the profile of the side-wall end portions of the gate electrode is improved.

The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film , the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing a semiconductor integrated circuit device having a capacitor

An SOG film obtained by heat-treating a polysilazan type SOG film at high temperature of about 800&deg; C. is used as a planarized insulating film to be formed on the gate electrode of a MISFET (Qs, Qn, Qp). A polysilazan SOG film not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers ( ).

Method of manufacturing semiconductor integrated circuit device having insulatro film formed from liquid containing polymer of silicon, oxygen, and hydrogen

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor integrated circuit device and process for manufacture the same

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing semiconductor integrated circuit device having a capacitor

A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating films are smoothed by a chemical mechanical polishing (CMP) method. The process of padding the connection holes with the metallic film is effected through a CVD or selective CVD method.

Semiconductor integrated circuit device and method for fabricating the same

Described is a process for manufacturing a semiconductor integrated circuit device, to expose semiconductor regions over the surface of a semiconductor substrate in self-alignment to wiring lines (including gate electrodes) and element isolating regions when forming connection holes. The process includes a first step of coating a semiconductor substrate with a first conductive film, a first insulating film and a second insulating film sequentially, and patterning these films to form first conductive film patterns. A third insulating film is then formed over the semiconductor substrate, on the side walls of the first conductive film patterns and over the second insulating film, and a fourth insulating film is formed over the third insulating film. After forming the third and fourth insulating films, a mask for a first opening between adjoining ones of the first conductive film patterns is formed over the fourth insulating film, and the fourth insulating film exposed from the first opening of the mask is etched, under conditions that the fourth insulating film is more easily etched off than the third and second insulating films, to form a second opening in the fourth insulating film. Thereafter, the third insulating film, as exposed through the second opening, is anisotropically etched under conditions that the third insulating film is more easily etched off than the first insulating film and the fourth insulating film, to form a third opening.

Process for manufacturing semiconductor integrated circuit device

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta,O,(tantalum oxide) film,the portions of bit lines BL and first-layer interconnect lines,to,of a peripheral circuit which are in contact with at least an underlying silicon oxide film,are formed of a W film, the bit lines BL and the interconnect lines,to,being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines,to,and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Semiconductor integrated circuit device, and method of manufacturing the same

Growing community of inventors

Hachiouji, Japan

Masayoshi Saito