Hitachi, Ltd.

Masayoshi Naito

Tsutomu Yatsuo

Masahiro Okamura

Hiroshi Okamoto

Yasuo Morooka

Naoki Tanaka

Takahiro Nagano

Takuzo Ogawa

Yoshio Terasawa

Masahiro Kayama

Kazuo Kato

Nobutake Konishi

Atsuo Watanabe

Takao Sasayama

Kenji Miyata

Shin-ichiro Umemura

Tatsuya Kamei

Hidekatsu Onose

Naohiro Momma

Jin Onuki

Michio Ohue

Hiroaki Okudaira

Fumio Sato

Tomio Yasuda

Mitsuo Yanagi

A chaotic character evaluating apparatus includes a processor for predicting future variation in sequential data and a processing for determining a degree of accuracy of the prediction, a processor for predicting variation of the sequential data in reverse and a processor for determining a degree of accuracy of the prediction, and a processing for comparing the degrees of accuracy with each other. If the degrees of the accuracy differ from each other, the variation of the sequential data is determined to be attributable to chaos, while when the degrees of accuracy are substantially equal to each other, the variation in the sequential data is determined to be attributable to noise. Further, a control apparatus for generating a control value from a feedback signal output from an object under control and having chaotic components eliminated is realized. Thus, it is possible to easily and accurately determine whether variation in the sequential data is attributable to chaos or noise.

Chaotic character evaluating apparatus and method of the same and

A control system is for accelerating stabilization of a chaotic state of a controlled system into a desired periodic state. In the control system, the SOGY algorithm is extended to permit selection of a region on a chaotic attractor as a target, so that the SOGY algorithm can be successfully combined with the OGY algorithm for the purpose of stabilization of the controlled system in the periodic state. Also, the method of nonlinear prediction is introduced so as to secure the effectiveness of the SOGY algorithm. Further, an uncertainty of prediction is taken into consideration so as to eliminate unnecessary control and to improve the effectiveness of the SOGY algorithm.

Control system

A semiconductor optical modulator is provided wherein very thin films of two kinds of semiconductors having different band gaps are laminated alternately to form a multi-quantum well (MQW) structure, also called a super-lattice structure, and current is injected into the MQW structure to change the corresponding optical absorption and refractive index characteristic thereof so that a sufficient on/off ratio can be obtained.

Semiconductor device for control of light

In a high-voltage thyristor comprising a semiconductor body having contiguous pnpn four layers, and opposed anode and cathode electrodes and a gate electrode provided for the semiconductor body, one of p-base and n-base regions having an impurity concentration higher than the other has an impurity concentration which is no more than 8.times.10.sup.15 atoms/cm.sup.3 in the vicinity of a junction between the one base region and an adjacent emitter region and which has a gradually decreasing gradient toward the other contiguous base region. The one base region has a sheet resistance of 500 to 1500 ohms/.quadrature.. The realization of a high-voltage, large-diameter and large-current thyristor can be ensured.

High voltage thyristor with optimized doping, thickness, and sheet

A switching device and circuit comprises a bipolar transistor and at least two field effect transistors for controlling the bipolar transistor. A first field effect transistor has its drain and source connected across the collector-base of the bipolar transistor and a second field effect transistor has its drain and source connected across the base-emitter of the bipolar transistor. Gates of the first and second field effect transistors are connected in common and supplied with a voltage signal. The first field effect transistor is of an enhancement type and the second field effect transistor is of a depletion type.

FET-bipolar switching device and circuit

A multi-emitter type semiconductor device, namely, a semiconductor device having an arrangement in which a majority of emitter regions are divided by a gate region and surrounded thereby. In the semiconductor device, a member adapted to apply an external control signal to a gate electrode takes the form of a closed-loop shape and the majority of emitter regions are arranged on both sides of the loop. This arrangement ensures that the individual emitter regions, even when the number of the emitter regions is increased to a great extent, can be applied with a uniform control signal, thereby preventing degradation of the turn-off characteristics.

Semiconductor devices of multi-emitter type

A light activated thyristor with high dv/dt capability is provided by disposing first and second thyristors, one a primary and the other a pilot thyristor, in a semiconductor body having first and second major surface. The two thyristors have common first emitter, first base, and second base regions, and have spaced apart second emitter regions adjoining the second major surface of the body. The second emitter region of the second thyristor consists of first and second portions, first portion abutting the second base region of the second thyristor to create a ratarded electrical field. An exposed portion of the second major surface at the second emitter region of the second thyristor activates the second thyristor when electromagnetic radiation of wavelengths corresponding substantially to the energy bandgap of the semiconductor body strikes this exposed portion. The cathode electrode makes ohmic contact with the second emitter region of the first thyristor, and the anode electrode makes ohmic contact with the common first emitter regions. A floating contact also makes ohmic contact to the second emitter region of the second thyristor and the common second base region between the thyristors.

Light activated semiconductor device

A novel structure of a high breakdown voltage semiconductor device has a pair of major surfaces on which a pair of main electrodes are formed and a PN junction formed between the pair of major surfaces with a side surface to which the PN junction is exposed being covered with a passivation material. An auxiliary electrode of a conductive member is provided, which is disposed externally of the peripheral edge of the major surface of the semiconductor substrate, and which contacts to the passivation material and is electrically connected to the main electrode. When a voltage for reverse biasing the PN junction is applied between the pair of main electrodes, ions in the passivation material are collected by an electric field established in the passivation material so that the deterioration of the breakdown on the surface of the semiconductor substrate is prevented.

High breakdown voltage semiconductor device

A field controlled thyristor is disclosed which comprises a first emitter region exposed to one main surface of a semiconductor substrate and having a first conductivity type, a second emitter region exposed to the other main surface of the substrate and having a second conductivity type, a base region connecting the first and the second emitter region, and a gate region provided in the base region. The gate region consists of a slab-like first portion disposed parallel to both the emitter and a second portion connecting the first slab-like portion with one of the main surfaces of the semiconductor substrate. The impurity concentration of the base region is higher in the portion of the base region nearer to the emitter region having the same conductivity type as that of the base region than in the portion of the base region nearer to the emitter region having the opposite conductivity type to that of the base region. The field controlled thyristor has a high forward blocking voltage gain (anode-cathode voltage/gate bias voltage), a large current rating, and a high switching power capability and its switching time is very short.

Field controlled thyristor with dual resistivity field layer

A thyristor comprising a four-layer semiconductor substrate of PNPN structure in which the sum of the thicknesses in the layered direction of the intermediate P-type and N-type layers is less than 400.mu., and the amount of impurities per unit area of either one of the outer P-type and N-type layers is less than 3.times.10.sup.14 atoms/cm.sup.2.

Thyristor having low on-state voltage with low areal doping emitter

A semiconductor device is doped with a multiple acceptor impurity having a monovalent energy level for forming a recombination center of carriers within the semiconductor body, and at least one multivalent energy level for capturing carriers within a depletion layer of a PN junction of the semiconductor body.

Growing community of inventors

Hitachi, Japan

Masayoshi Naito