Kabushiki Kaisha Toshiba

Pioneer Corporation

Masayoshi Murayama

Fumitaka Sato

Shigekazu Sumita

Shimpei Kunii

Shizuo Kamio

Hiroshi Kida

Akihito Yamada

Kensuke Adachi

Shigehiro Kajihara

Masaaki Saito

Noriyo Fujii

Tsutomu Ohtani

Hiromichi Tome

According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the VDS mode, an FDS phase register which holds a phase shift amount in the FDS mode, a mode setting unit configured to indicate in which of the VDS mode and the FDS mode data is sampled, a sampling position setting unit which selects the phase shift amount set in one of the VDS and the FDS phase register in accordance with a setting value of the mode setting unit, and provides the selected phase shift amount as a sampling position, and a clock phase shift unit which shifts a phase of an input clock signal in accordance with the shift amount, and provides the shifted input clock signal as a sampling clock.

Host controller, semiconductor device and method for setting sampling phase

One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Sampling phase correcting host controller, semiconductor device and method

According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Host computer, computer terminal, and card access method

According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

An electronic program table processing apparatus can obtain the number of receivable channels M and the standard number of channels N displayable on one screen. When EPG display data is generated, the apparatus examines whether or not the number M is smaller than the number N. If so, the apparatus generates the EPG to display the program information for M channels on one screen. If not, the apparatus generates the EPG to display the program information for N channels on one screen.

Apparatus for and method of processing electronic program table, and computer program product

A coordinate position detecting method uses a plurality of light emitting elements and a plurality of light receiving elements located on mutually opposite sides, all the elements being arranged at a predetermined interval in horizontal and vertical directions, with each pair of mutually opposed light emitting element and light receiving element forming a light beam path, such that the coordinate position of a light blocking object can be detected once the light beam path is blocked. The method comprises: storing N previous coordinate datas obtained when detecting a movement of the light blocking ojecte, using n (1&lE;n&lE;N) coordinate datas of the N previous coordinate datas to calculate a coordinate position of the light blocking object; and changing the number of the coordinate datas for use in calculating the coordinate position, in accordance with a speed of the movment of the light blocking object.

Coordinate position detecting method and display apparatus using the same

For each of multiple segments acquired by dividing a binary image by a predetermined under of lines, image data of a reference line corresponding to a start line of that segment is stored in an intermediate start table in association with data indicating a head coding position of the start line in code data acquired when the binary image is compressed. Based on the stored data, partial image extraction is executed.

System and method of extracting binary image data

In processing of a minimizer average error method (or an error diffusion method), a threshold value for determining whether a point (pixel) as an object to be processed is a black or white dot is changed in accordance with the pixel position using a threshold value matrix having a two-dimensional repetitive pattern. When a one-dot size in an output apparatus which can only perform binary expression in units of pixels is larger than a logical size, a continuous tone image is converted into a pseudo half tone image in consideration of an increase in size of a dot into other dots (projecting portions).

System and method for converting continuous half tone image into pseudo

An information processing apparatus includes a hinge mechanism for rotating an integral type hand writing input/display device and a keyboard from a position, in which the display surface of the integral type hand writing input/display device and the surface of the keyboard face each other, to a position of a desired opening angle. The input/display device is provided on a top portion of a processing apparatus body, is constituted by integrally superposing a tablet device for coordinate input on a display surface of a display device, and inputs coordinate data representing a location indicated voluntarily on the tablet device. The hinge mechanism can retain the desired opening angle. There are further provided an attitude sensor for detecting which of the integral type hand write input/display device and the keyboard is situated substantially horizontally, and a changing circuit for changing the display contents of the integral type hand write input/display device and coordinate data detection location, in accordance with the ON/OFF state of the attitude sensor.

Computer having integral type hand writing input/display device and

When a variable length code requires two cycles in decoding, portions of code bit strings serving as objects to be decoded in first and second cycles of the variable length code are caused to overlap each other. In the first cycle, a non-overlapping portion is determined as a decoded portion. A length of a code bit string actually decoded in the first cycle is determined as a length of the code bit string serving as the object to be decoded in the first cycle excluding the length of the overlapping portion so as to determine a start position of the code bit string serving as the object to be decoded in the second cycle.

Variable length code parallel decoding apparatus and method

According to a binary data expansion processing apparatus of this invention, unicolor image data is generated in a generation section in accordance with data associated with a run length and a color instruction for designating the color of image data to be generated. Unicolor image data exceeding the generated set is combined following the already-generated image data portion in accordance with a point a0, thus generating image data for a byte block of interest. At the same time, a color change point on a reference line corresponding to the byte block of interest is detected by a b1 detector. It is checked from the detected color change point if the combined image data exceeds a byte length. If the combined image data exceeds the byte length, the combined image data for one byte of the combined image data is output to an external device.

Growing community of inventors

Tokyo, Japan

Masayoshi Murayama