Matsushita Electric Industrial Co., Ltd.

Masayoshi Hirashima

Shin Fukuda

Hidemi Henmi

Hiroki Monta

Noriaki Omoto

Toshiro Nozoe

Osamu Shizuya

Akira Yamashita

A time serial signal from a signal source is input into a delay circuit, and the signal is read out from arbitrary intermediate taps of the delay circuit to obtain a specific delayed signal. Alternatively, a time serial signal from a signal source is allotted to a plurality of memory circuits, and the allotted signal contents are read at a specific moment to obtain a specific delayed signal. By distributing the delayed signals in this manner, a signal distribution apparatus can send a serial signal, from its beginning with little delay, to multiple terminals requesting the signal at arbitrary times.

Signal distribution apparatus for a directional signal transmission

A program table displaying apparatus includes a display controlling apparatus for displaying a program table for a plurality of programs in a table on a display. The table has a horizontal row with a channel number identifying a channel corresponding to one of the programs and a vertical row with a time number for the channel. The television program table is derived from a plurality teletext broadcasts. Also included is a program reserving apparatus for reserving a desired program by selecting one of the programs. A time comparing apparatus is further provided for comparing a current displayed time frame and the time number for the channel to determine if there is a corresponding program for the displayed time frame. Further provided is a minute information extracting device for extracting minute data corresponding to said corresponding program. A program title extracting apparatus is also included for extracting a program title corresponding to the corresponding program and a number of rows calculating apparatus is provided for calculating a number of rows from the minute data and the number of letters in the program title. Finally, a time frame determining apparatus is included for determining a corresponding time frame from the calculated number of rows.

Program table displaying apparatus

A common circuit is used for scrambling and descrambling video signals. A memory stores key data. During scrambling the output of the memory is transmitted to a read address counter through an address generating circuit. Scrambling is effected by executing line rotation from a cut point. Descrambling is effected by the reverse of the aforementioned process.

Video signal scrambling and descrambling apparatus

A scramble codec comprises a latch means for holding an ID number for securing television or other communication data, a pair of memories which can be alternately loaded with input communication data signals in a predetermined cycle, a shift register which is initialized with the ID number held by the latch means to output dissimilar pseudorandom pulse signals in a predetermined cycle, an address setting circuit which sets, as the initial value, a value corresponding to the output of the shift register in scrambling and a value obtainable by subtracting the output of the shift register from the maximum address value of the memories in descrambling, and an address counter which reads communication data from the address designated by the address setting circuit. The above scramble codec has both the function of a decoder for scrambled communication data and the function of an encoder for scrambling communication data, is simple in construction and compact and features improved security. The scramble codec, as such, can be easily built into a receiver such as a television receiver to provide, for example, a television receiver which does not only function as an information receiver but can be used in combination with a VTR or other recording device for the mutual transmission and reception of communication data with security fully retained. Further improvement in security is obtained when the above scramble codec further comprises a nonvolatile key data memory for holding a specified key data and an EOR circuit which takes the exclusive logical sum of the ID number data held by the latch means and the output of the key data memory, with the output of the EOR circuit being set as the initial value in the shift register which outputs dissimilar pseudorandom pulse signals in a predetermined cycle.

Scramble codec and a television receiver incorporating the same

Television signal processor having means for comparing and deleting

This invention, relating to a unidirectional television system such as satellite television broadcasting system, is intended to transmit and receive the charging information corresponding to the content of the program being transmitted in the digital form at certain time intervals, and account the amount by a charging amount accounting means built in the receiver from said information and the time of receiving the television program, write the charge data proportional to the amount in a memory, read out the charge data in the memory when necessary, and display it on a display means.

Pay television system

A satellite TV receiver for receiving a satellite broadcasting, wherein neighboring televison signals are vertical and horizontal polarized waves, and wherein a polarizer for the satellite receiver controls an antenna so that the polarization plane of the antenna is adapted to the polarization plane of television signal to be received. The receiver further includes a narrow band-pass filter for rejecting terrestrial interference so that the desired polarization plane can be more easily determined.

Satellite receiver having improved polarization plane determination means

A television sound signal processing apparatus receives a digitized delta-encoded sound signal superposed in a horizontal blanking period and a digital signal showing the standard value of the sound signal superposed in a vertical blanking period, and then compares the reference signal of this field with that of one field before, and, when the difference is greater than a predetermined value, employs the decoded value of the delta encoded signal immediately before that reference signal as the standard value for the delta decoding of the sound signal.

Television sound signal processing apparatus

A teletext decoder having a character pickup circuit superior in the antinoise property and response characteristic by allowing signals only in the vicinity of clock run-in signals to pass, simultaneously detecting the amplitude of clock run-in signals through a band-pass filter circuit, gating framing code signals and reproduced clock and slice data, and integrating and holding the clock run-in signals.

Teletext decoder

A signal processing system in a transmission system like Teletext System in which a binary signal is superimposed on a television signal for transmission is disclosed. When the binary signal is received, an upper (or lower) level of a pilot signal in the binary signal is clamped to a first reference voltage by a clamp circuit while the amplitude of the pilot signal is controlled by a variable gain amplifier such that the lower (or upper) level of the pilot signal becomes equal to a third reference level. The binary signal is then amplitude-discriminated using a second reference voltage as a discrimination reference. In this manner, the binary signal is correctly converted to a digital signal.

Multiplexed television signal processing system

Improved sampling clock reproducing apparatus for receiving digital signal which is superimposed in the television signal during a vertical blanking interval. The sampling clock signal is made by selectively gating a pilot signal from the superimposed signal, obtaining a square thereof, then passing it through a resonance circuit with a resonance frequency twice a repetition frequency of the pilot signal. Thus, the sampling clock signal of the frequency twice the repetition frequency of the pilot signal is obtainable without digital processing attaining high durability against noises.

Sampling clock reproducing apparatus

A system for receiving a bi-level information signal multiplexed with a television signal or the like comprises a receiving circuit for receiving the television signal on which the bi-level information signal such as a still image video signal is superimposed during a vertical retrace period, an upper level detecting circuit for detecting an upper level of a start signal indicative of a reference phase and a reference amplitude inserted at a leading portion of the information signal and a lower level detecting circuit for detecting a lower level of the start signal. In response to output signals from the upper and lower limit detecting circuits, a slicing level of a slice circuit to which the information signal is fed is automatically controlled to a predetermined level so that the waveform is always reshaped at an exact slice level regardless of variations in the transmitted information level in order to assure exact reproduction of the information signal.

Multiplexed information signal receiving system

A sampling clock reproducing device wherein binary coded signals representative of letters or other patterns which are superimposed on the television signal and the pilot signal superimposed before the binary coded signals in order to indicate the phase thereof are received, and the phase of the pilot signal is detected whereby clock pulses for sampling the binary coded signals are reproduced.

Growing community of inventors

Ibaraki, Japan

Masayoshi Hirashima