Fujitsu Microelectronics Limited

Masayasu Hojo

Satoshi Masuda

Naofumi Kobayashi

Ryuji Shimizu

Hideaki Konishi

Haruhiko Abe

In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

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Kawasaki, Japan

Masayasu Hojo