Seiko Epson Corporation

Saiko Epson Corporation

Masaya Uehara

Satoru Kodaira

Eitaro Otsuka

Koji Miyashita

Hitoshi Kobayashi

Takeshi Kumagai

A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits, which is different from the latch circuit to which the data are formerly latched, included in the group of latch circuits corresponding to the same read amplifier; and the latched data are lastly outputted in a desired order from each of the latch circuits having the latched data.

Semiconductor memory device having a plurality of latch circuits coupled to each read amplifier

A semiconductor device having a plurality of memory cells for storing data, an address input circuit having an address signal generation section for independently generating an address signal using a clock signal in a test mode, and a delay circuit for delaying an input time of the address signal from the address input circuit to a subsequent circuit for a predetermined time period which is equal to or longer than the time necessary for the generation of the address signal.

Semiconductor device, method of testing the same and electronic instrument

A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signal. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.

Growing community of inventors

Chino, Japan

Masaya Uehara