Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Texas Instruments Corporation

Hitachi Ulsi Engineering Corp.

Elpida Memory, Inc.

Hiachi, Ltd.

Masaya Muranaka

Yukihide Suzuki

Hiromi Matsuura

Hidetoshi Iwai

Kanehide Kenmizaki

Yasushi Takahashi

Kazuyuki Miyazawa

Makoto Morino

Tetsuya Kitame

Shinichi Miyatake

Masamichi Ishihara

Yoshihisa Koyama

Hidetomo Aoyagi

Yutaka Ito

Hiroyuki Uchiyama

Ryoichi Hori

Hisashi Nakamura

Satoshi Oguchi

Shigetoshi Sakomura

Haruo Ii

Takeshi Kizaki

Shunichi Sukegawa

Hideaki Kato

Toshitugu Takekuma

Kazumasa Yanagisawa

Katsutaka Kimura

Yoshinobu Nakagome

Hitoshi Tanaka

Shoji Kubono

Toshiyuki Sakuta

Sinichi Miyatake

Takumi Nasu

Shoji Wada

Masahiro Ogata

Yoshitaka Kinoshita

Kyoko Ishii

Masahiro Katayama

Nobuhiko Ohno

Eiji Yamasaki

Toshitugu Takemuma

Satoru Koshiba

Seiichi Shundo

Shiyuzo Shiozaki

Yasunori Orito

Osamu Okayama

A random number generating method for an electronic device including a plurality of unit circuits each first and second logic circuits, each logic circuit having a same shape and being formed through a same fabrication process, and an amplifier circuit for forming a binary signal by amplifying a noise superposed on the differential voltage of threshold voltages of the first and the second logic circuits; and a signal variation detecting circuit for forming an output signal in response to a variation in any of a plurality of binary signals outputted from the plurality of unit circuits, wherein a plurality of binary signals outputted from the signal variation detecting circuit are combined to generate a random number.

Random number generating method and semiconductor integrated circuit device

In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

An error rate select circuit activated in an information sustaining mode is provided, wherein a plurality of pieces of data are read from a dynamic memory circuit and inspection bits which are used to detect an error existing in the pieces of data are generated. If no error is detected, a first predetermined value is added to a total value. If an error is detected, a second predetermined value greater than the first predetermined value is subtracted from the total value. If the total value exceeds a first set value, a refresh period is lengthened by a predetermined time increment. If the total value becomes smaller than a second set value, the refresh period is shortened by the predetermined time increment.

Method of deciding error rate and semiconductor integrated circuit device

This invention provides a signal transfer technique capable of realizing stable high rate data transfer and the reduction of a layout area. A system (semiconductor device) for realizing a high rate data transfer circuit method includes: a transmission circuit which consists of a normal signal transmitter and a receiving amplifier starting signal transmitter; a receiving circuit which consists of a receiving amplifier and a receiving amplifier starting signal receiver; a normal signal line and a receiving amplifier starting signal line connected between the transmission circuit and the receiving circuit; and the like. The normal signal transmitter includes a circuit which changes an output level for a specific period in accordance with the level of a normal signal and a circuit which controls the normal signal line to allow the normal signal line to function between VDD and VSS. The receiving amplifier includes a capacitance and a circuit which fetches a voltage of the capacitance at predetermined change timing of a control signal and then outputs a signal based on the fetched voltage of the capacitance. The receiving amplifier consists of a chopper comparator, and the normal signal line consists of a single transmission path.

Signal receiving circuit, semiconductor device and system

A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with a computing circuit for generating an address signal for test; a packet decoder for designating the kind of computation to the computing circuit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.

Semiconductor storage device and test system

There is provided an error rate select circuit activated in an information sustaining mode, wherein data is read out from a memory circuit comprising dynamic memory cells and inspection bits for detection and correction of an error. If no error is detected, a first detection signal is accumulated in a first direction, that is, the first detection signal is added to a sum. If an error is detected, a second detection signal is accumulated in a second direction, that is, the second direction signal is multiplied by a weight to produce a product before subtracting the product from the sum. If the sum increases in the first direction, exceeding a predetermined value, the refresh period is lengthened by a predetermined incremental time. If the sum decreases in the second direction, becoming smaller than another predetermined value, the refresh period is shortened by a predetermined decremental time.

Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

Semiconductor memory device and memory system

Memory cells are used which each have a MOSFET that holds an information voltage of three or more values at its gate, a writing transistor that supplies the information voltage of three or more values to the gate of the MOSFET, and a reading transistor connected in series with the MOSFET. A plurality of reference voltages corresponding to the information voltage of three or more values are applied from a source line to the sources of the MOSFETs, so that digital data is produced by a combination of on-state/off-state of the MOSFET and the plurality of reference voltages or that the source voltages themselves of the MOSFETs are produced as read voltages.

Semiconductor memory device having memory cells each capable of storing three or more values

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

Growing community of inventors

Akishima, Japan

Masaya Muranaka