Fujitsu Corporation

Fujitsu Limied

Masaya Kibune

Hirotaka Tamura

Hisakatsu Yamaguchi

Sanroku Tsukamoto

Takayuki Shibasaki

Takuji Yamamoto

Yasumoto Tomita

Xuan Tan

A method of generating a neural network may be provided. A method may include applying non-linear quantization to a plurality of synaptic weights of a neural network model. The method may further include training the neural network model. Further, the method ma include generating a neural network output from the trained neural network model based on or more inputs received by the trained neural network model.

Quantization of neural network parameters

An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.

A/D converter and A/D converter calibrating method

A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.

Receiver circuit and receiving method

A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.

Duty ratio correction circuit, double-edged device, and method of correcting duty ratio

A signal transmission method suppresses a reflected wave of a transmission signal on a transmission line, by obtaining level and time information related to the reflected wave by computing a correlation between a data pattern of the transmission signal and the reflected wave, and correcting a waveform of the transmission signal based on the level and time information related to the reflected wave.

Signal transmission method, transmission circuit and apparatus

A receiver circuit includes: an equalization circuit that equalizes a first signal to obtain a second signal, and adjusts a characteristic of an equalization in accordance with an error between the second signal and a third signal; and a first offset adjustment circuit that adjusts an offset of the first signal in accordance with an error signal indicating the error.

Receiver circuit, method of adjusting offset, and transmission/reception system

A reception circuit includes: an AD converter; an equalization circuit that equalizes an output of the AD converter; a determination circuit to which error information is input from the equalization circuit; and a controller that adjusts at least one of resolution and voltage range of the AD converter, in the circuit the determination circuit outputs a control signal to adjust at least one of resolution and voltage range to the controller based on the error information.

Reception circuit, reception method, and signal transfer system

An integrated circuit includes a bypass signal path exchanging, between transceivers which are included in the integrated circuit, a signal transmitted/received between a transceiver of the transceivers and an internal logic circuit which processes data being input/output by transceiver with bypassing the internal logic circuit, a switch switching a pathway of the bypass signal path, and a switch changeover controller transferring a switch control signal that performs a changeover of the switch.

Integrated circuit including bypass signal path

A receiver that receives a train of a plurality of symbols representing digital data, includes: an isolated pulse detector that detects whether the digital data includes an isolated pulse in the symbol train, respectively; a phase detector that detects a timing at which the level of the symbols changes; a symbol value converter that converts the symbols into logical values on the basis of the timing detected by the phase detector; and a data selector that selects a logical value of the isolated pulse instead of the logical value converted by the symbol value converter when the isolated pulse detector detects the digital data containing the isolated pulse.

Receiver

A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

Receiving circuit and sampling clock control method

A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.

Clock generation circuit and system

A reception circuit includes: an AD converter that outputs digital data in accordance with an input signal; a correction circuit that corrects nonlinearity of the AD converter; and an equalization circuit that equalizes the corrected digital data, wherein the correction circuit includes: a conversion table used to convert digital data output from the AD converter; and a correction amount computation circuit that creates the conversion table from the output data of the AD converter and the output of the equalization circuit. The correction amount computation circuit creates the conversion table so that there is no dependence between the ADC output value of the AD converter and the estimation result by the equalization circuit for the ADC output value.

Reception circuit, method of creating AD converter conversion table of reception circuit, and signal transfer system

A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.

Data recovery circuit, data recovery method and data receiving apparatus

An AD converter includes a first amplitude circuit, a second amplitude circuit, and a determination circuit. A control signal line controls a first amplitude gain of the first amplitude circuit and a second amplitude gain of the second amplitude circuit.

AD converter, data receiver and data reception method

An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal responsive to the first signal and the second signal, an operation test circuit having substantially an identical circuit configuration to the input and output circuit, and configured to receive the first signal from the signal generating circuit and a third signal to generate an output signal responsive to the first signal and the third signal, a check circuit configured to generates a check signal indicative of an operating condition of the operation test circuit in response to the output signal of the operation test circuit, and an adjustment circuit configured to adjust the signal generating circuit in response to the check signal output from the check circuit.

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Kawasaki, Japan

Masaya Kibune