Sony Corporation

Masatoshi Yano

Hiroshi Ishida

Shumpei Kohri

Hideki Usuki

Kazuo Watanabe

A static random access memory (SRAM) includes a pair of p-channel metal-oxide-semiconductor (PMOS) transistors which serve as variable resistors for terminating bit lines and a control circuit for causing the PMOS transistors to have a low impedance level during read out and an intermediate impedance level during writing so that sudden d.c. current is suppressed and the voltage at the bit lines is prevented from being lowered. The variable resistor device can constitute a current mirror circuit along with a metal-insulator-semiconductor (MIS) transistor of the control circuit, so that it becomes possible to provide a stable control which is invulnerable to manufacturing tolerances.

Memory with a variable impedance bit line load circuit

A delay circuit for integrated circuits includes a current mirror circuit having at least a pair of MIS transistors, a constant current source and a capacitance. The delay time is determined by the charging time of the capacitance connected to one of the MIS transistors. A stable delay time is obtained regardless of manufacturing variations and the space required for the circuit is reduced.

Delay circuit for integrated circuit

A memory circuit incorporates a plurality of memory cells arranged in matrix form, with a data line drive circuit having an active load circuit including two MOS transistors, operating as resistive elements during writing, and connected to the data line and the inverted data line of the cells. A differential amplifier is connected to the data line and inverted data line, and a plurality of constant current sources are connected to the transistors of the differential amplifier, with switching means causing one constant current source to be nonconductive during a write operation, with at least one of the current sources being normally on during reading and writing.

Growing community of inventors

Kanagawa, Japan

Masatoshi Yano