Nippon Telegraph and Telephone Corporation

Ntt Electronics Corporation

Ntt Innovative Devices Corporation

Ntt Corporation

Nippon Telephone and Telegraph Corporation

Masatoshi Tobayashi

Yoshikazu Urabe

Makoto Nakamura

Tadashi Minotani

Masahiro Endo

Masafumi Nogawa

Toshiki Kishi

Hideyuki Nosaka

Koichi Murata

Hiroyuki Fukuyama

Shinsuke Nakano

Kimikazu Sano

Eisuke Tsuchiya

Hatsushi Iizuka

Masaki Hirose

Hiroshi Koizumi

Shunji Kimura

Hiroaki Katsurai

Yuhki Imai

Yukio Akazawa

Jun Endou

Yohtaro Umeda

Hiroaki Sanjoh

Yasunobu Inabe

Yuji Akatsu

Shigehiro Kurita

Nobuhiro Toyoda

Yuuki Imai

Eiji Hyodo

Yasuhito Takeo

Yasuhiko Takeo

The transmission interface includes a plurality of transmitters, wherein the transmitters are provided with: a power supply terminal shared by the plurality of transmitters, configured to receive a ground voltage; a bias terminal configured to receive a bias voltage; signal terminals configured to receive a signal voltage; a power supply fluctuation inverting bias unit to which a ground voltage and a bias voltage are applied, and which outputs the ground voltage making its fluctuation 180 degrees out of phase; a modulation unit to which the output of the power supply fluctuation inverting bias unit and a signal voltage are applied, and which outputs the opposite phase ground voltage making its fluctuation in phase; and a laser diode to which the ground voltage and the output of the modulation unit are applied.

Transmission interface and transmitter

An embodiment is a connecting circuit connected to the preceding stage of a transmission circuit and configured to receive a baseband signal, includes an isolation element connected between an input terminal and an output terminal, a signal midpoint detection circuit connected parallel to the isolation element, a bias adding circuit connected in series with the signal midpoint detection circuit, and an initial voltage value detection circuit connected to a frame detection circuit. The initial voltage value detection circuit holds an initial voltage value of the baseband signal in accordance with the signal of the frame detection circuit, and outputs the initial voltage value to the signal midpoint detection circuit. The signal midpoint detection circuit detects a midpoint voltage from the baseband signal and the initial voltage value, and outputs the midpoint voltage to the bias adding circuit. The bias adding circuit adds the midpoint voltage to a bias voltage.

Connecting circuit and communication interface

An amplifier circuit includes: an amplifier connected to an isolating element; a signal midpoint detecting circuit connected in parallel with the isolating element; a bias adding circuit connected in series with the signal midpoint detecting circuit; and an initial voltage value detecting circuit connected to the frame detecting circuit. The initial voltage value detecting circuit holds an initial voltage value of the baseband signal using a signal from the frame detecting circuit, and outputs the initial voltage value to the signal midpoint detecting circuit. The signal midpoint detecting circuit detects a midpoint voltage from the baseband signal and the initial voltage value, and outputs the midpoint voltage to the bias adding circuit. The bias adding circuit adds the midpoint voltage to a bias voltage for biasing the baseband signal. The amplifier amplifies the baseband signal.

Amplifier circuit

An amplifier applied to TIA is provided to suppress the noise caused by a current source. An amplifier constituting a transimpedance amplifier includes an inductor element inserted between a current source connected to an input terminal of an amplification stage and a power source voltage line. The current source includes a first transistor in which a base terminal is connected to a current control bias and a collector terminal is connected to the input terminal. The inductor element is inserted between the emitter terminal of the first transistor and the power source voltage line.

Amplifier

An amplifier typically exemplified by a TIA is realized that provides an optimal band characteristic, that reduces the possibility of the oscillation, and that achieves a reduced dispersion of the band characteristics. An amplifier for amplifying an electric signal, comprising: a first buffer for amplifying the electric signal; a filter that is connected to an output of the first buffer and that includes a parallel circuit consisting of an inductor and a first capacity; and a second buffer connected to an output of the filter.

A transimpedance amplifier circuit () includes an amplifier () that amplifies a received signal, an automatic gain control (AGC) circuit () that controls the amplification gain of the amplifier by a first time constant in accordance with the level of the received signal, and a first selection circuit () that selects the first time constant from a plurality of predetermined values. This can simultaneously implement a short time constant of an AGC function necessary to instantaneously respond to a burst signal and a long time constant of the AGC function necessary to obtain a satisfactory bit error rate (BER) characteristic in a continuous signal by an inexpensive and compact circuit arrangement.

Transimpedance amplifier circuit

In an automatic gain control circuit, a peak detection circuit detects and outputs the peak voltage of an output signal from a variable gain circuit. An average value detection/output amplitude setting circuit detects the average value voltage of an output signal from the variable gain circuit, and outputs a calculated voltage. An amplification circuit controls the gain of the variable gain circuit by amplifying the difference between the output voltages of the peak detection circuit and average value detection/output amplitude setting circuit. The number of base-emitter junctions of transistors on a path in the peak detection circuit from input ports which receive output signals from the variable gain circuit to an output port which outputs a voltage to the amplification circuit is equal to the number of base-emitter junctions of transistors on a path in the average value detection/output amplitude setting circuit.

Automatic gain control circuit

In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.

Signal output circuit

A receiving method according to the present invention adjusts a level of an output voltage signal by switching a gain to be used for converting an inputted current signal to a voltage signal, in a preamplifier. Performing offset compensation on the output voltage signal in an offset compensator, in a post amplifier. Adding a reset signal, whose polarity is made opposite to a polarity of the output voltage signal, to the output voltage signal, in the preamplifier. Detecting the reset signal having added to the output voltage signal, and resetting the offset compensator by use of the detected reset signal, in the post amplifier.

Receiving method and receiving circuit

A gain switching determination circuit () compares/determines a comparative input voltage (Vc) from an inter-stage buffer () with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.

Transimpedance amplifier

In a phase sync circuit () which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit () of a dual loop configuration including both a phase comparison circuit () and a frequency comparison circuit (), a phase sync circuit () capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately &#xbc; period from the clock signal Ca and the data signal D are input to the frequency comparison circuit () to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D. This logical value is fed back by a frequency comparison loop Fto bring the frequency of the clock signal CK close to the bit rate of the data signal D without requiring any reference clock signal, thus achieving both broadening of the capture range and extraction of a high-quality clock signal.

Phase synchronization circuit

A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminalof a multiplier circuitapproaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

Growing community of inventors

Isehara, Japan

Masatoshi Tobayashi