Matsushita Electric Industrial Co., Ltd.

Masatoshi Tanaka

Kenshi Taniguchi

Noboru Mizuguchi

Kiyoshi Uchimura

Tomotaka Takeuchi

Seiho Kitaji

The present invention provides a video and audio signal multiplex transmitting apparatus having a video and audio signal multiplex sending apparatus for grouping audio data to packets of a fixed length in the sending side, and multiplexing video and audio signals by multiplexing horizontal and vertical phase signal outputs from horizontal and vertical counters that are in synchronization with a video signal to an audio data as video phase information, and a video and audio signal multiplex receiving apparatus provided with an audio packet interpolating device for separating the signal received to video and audio signals, detecting, if any audio data is lost, a lost audio data from a data block number of the audio data and audio clock phase information, and recovering an audio clock by means of horizontal and vertical counters and the clock phase information transmitted.

Video and audio signal multiplex sending apparatus, receiving apparatus

A video data transmitter includes: chrominance-data multiplexer which multiplexes parallel data obtained by digitizing a chrominance signal Pb, which is a component signal of an analog HDTV video signal, with parallel data obtained by digitizing a chrominance signal Pr; a word multiplexer which multiplexes parallel data obtained by digitizing a luminance signal Y, which is a component signal of analog HDTV video signal, with the output data of the chrominance-data multiplexer, and a parallel-to-serial converter which converts the parallel data output from the word multiplexer. A video data receiver includes a serial-to-parallel converter which converts received serial data into parallel data and a word separator which separates the output data of the serial-to-parallel converter into parallel data in the Y channel and parallel data in the Pb/Pr channel.

Video-data transmitter, video-data receiver, and video-data transceiver

An HDTV signal transmission system for sending a 10-bit-parallel YPbPr-format HDTV signal converted to ten C4 containers, and further to the SDH (a new synchronous digital network) STM-16 frame for transmission based on CCITT recommendations. The system includes a transmitter and receiver. The transmitter has time dividers for time-based dividing the HDTV signal into eight separated video signals, a C4 container device for multiplexing the eight separated video signals to ten C4 containers, and a STM-16 framing device for reformatting the ten C4 containers to the STM-16 frame. The receiver has an STM-16 deframing device for separating the ten C4 containers from the STM-16 frame, a C4 de-container device for demultiplexing the ten C4 containers to eight separated video signals, and time-division multiplexers for time-division multiplexing the separated video signals to the 10-bit-parallel YPbPr-format HDTV signal.

HDTV signal transmssion apparatus

A frame synchronizing apparatus is disclosed which includes a serial-parallel converter for converting input serial data into parallel data of a plurality of channels; a plurality of intra-channel synchronization detecting circuits each for detecting a synchronization pattern and a pseudo-synchronization pattern in one channel, and generating a channel synchronization detect signal and a pseudo-synchronization detect signal in one channel; a plurality of bit-shift error pattern detecting circuits each for detecting a bit-shift error pattern in one channel, and generating a bit-shift error pattern signal in one channel; a synchronization/bit-shift error detecting circuit for detecting a synchronization between channels and specifying the amount of erroneously shifted bits, and generating a frame synchronization detect signal and bit-shift error detect signals; and a bit-shift signal generating circuit for calculating the number of erroneously shifted bits in the serial-parallel converter based on the bit-shift error detect signals and the bit-shift error pattern signals, and generating a bit-shift signal to be supplied to the serial-parallel converter, whereby bits of the calculated number are shifted.

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Kashihara, Japan

Masatoshi Tanaka