Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Eastern Japan Semiconductor, Inc.

Other

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Eastern Technology Corp.

Masatoshi Morikawa

Isao Yoshida

Yutaka Hoshino

Tomoyuki Miyake

Shuji Ikeda

Shiro Kamohara

Megumi Kawakami

Fumitaka Nakayama

Tetsuo Uchiyama

Tetsuaki Adachi

Yoshikuni Matsunaga

Toru Fujioka

Osamu Kagaya

Kenji Sekine

Hitoshi Akamine

Yasuhiro Nunogawa

Masahito Numanami

Tsuyoshi Shibuya

Mineo Katsueda

Makoto Hatori

Nobuyuki Sugii

Katsuyoshi Washio

Masao Kondo

Yasuhiko Kokami

Masao Hotta

Kunio Seki

Terumi Sawase

Satoshi Goto

Kozo Sakamoto

Takeaki Okabe

Kouzou Sakamoto

Shigeo Ohtaka

Kenichi Nagura

Hideki Tsunoda

Mio Shindo

In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

Semiconductor device

In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs(P) for leading out electrodes on a source region, a drain regionand leach-through layers(), to which a first layer wirings(M) are connected and, further, backing second layer wiringstoare connected on the conductor plugs(P) to the first layer wirings(M).

Semiconductor device including a power MISFET

Semiconductor device including a power MISFET and method of manufacturing the same

A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Semiconductor device and manufacturing the same

To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an ntype drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an ntype offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

Semiconductor device and a method of manufacturing the same

Semiconductor device having a plurality of misfets formed on a main surface of a semiconductor substrate

Multilayered semiconductor structure containing a MISFET, a resistor, a capacitor, and an inductor

A semiconductor device includes a transmission power amplifier having cascaded MOSFET amplification stages disposed over a main surface of a semiconductor substrate. A CMOSFET control circuit controls the amplification stages. A first capacitor is also provided having upper and lower metal film electrodes formed over the main surface of the semiconductor substrate. The amplification stages are electrically coupled to one another via an inter-stage matching circuit which includes the first capacitor.

In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs(P) for leading out electrodes on a source regiona drain regionand leach-through layers(), to which a first layer wirings(M) are connected and, further, backing second layer wiringstoare connected on the conductor plugs(P) to the first layer wirings(M).

Power mosfet having conductor plug structured contacts

A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).

High frequency power amplifier module, and wireless communication system

Plural elements forming a high frequency device in one chip are provided by forming a resistor element and the lower electrode of a capacitor element from one identical polycrystal silicon film over a substrate; forming the gate electrode of a power MISFET, upper electrode of the capacitor element, gate electrode of an n-channel type MISFET and gate electrode of a p-channel type MISFET from an identical polycrystal silicon film different from the other polycrystal silicon film and a WSi film; forming a capacitor element having a wiring formed on a silicon oxide film deposited over the substrate as a lower electrode and a wiring formed on the silicon oxide film as the upper electrode in the region MIN; forming a spiral coil in a region IND using an aluminum alloy film identical with that deposited on a silicon oxide film; and forming a bonding pad in a region PAD.

Semiconductor device including multiple wiring layers and circuits operating in different frequency bands

Growing community of inventors

Hanno, Japan

Masatoshi Morikawa