Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Spansion Llc.

Fijitsu Limited

Masatoshi Kokubun

Shinya Udo

Chikara Tsuchiya

Takashi Matsumoto

Seiji Yamagata

Toshihiko Kasai

Katsuyosi Yamamoto

Jun Funakoshi

Yoshihiro Kizaki

Masao Kumagai

Mayo Kitano

Takeo Shigihara

Hidekazu Nishizawa

Hiroshi Kobayashi

Hidenobu Ito

Toshitaka Mizuguchi

Asao Kokubo

Shigeru Nishio

Kenji Kato

Katsuyuki Yasukouti

A charging circuit includes a monitoring part configured to monitor a battery voltage applied to a battery and configured to output an overvoltage signal when the battery is in an overvoltage condition a protection part configured to electrically disconnect the battery from an adaptor when receiving the overvoltage signal, and a switch which, when the battery is electrically disconnected from the adaptor, switches a monitoring node for an adaptor voltage outputted from the adaptor, from a supply node of the battery voltage to a supply node of a system voltage, which is applied to a system electrically connected with the battery and the adaptor, based on the overvoltage signal to cause a control command for controlling the adaptor voltage based on the system voltage to be outputted.

Charging circuit, charging apparatus, electronic equipment and charging method

A voltage control method includes producing an error signal based on a difference between a reference signal and an adaptor voltage and an adaptor current corresponding to the adaptor voltage, regulating, based on the error signal, the adaptor voltage, comparing a reference voltage to a voltage proportional to a potential corresponding to an identifying voltage corresponding to the adaptor voltage, detecting, based on the comparison result, whether or not a couplable external power source is suitable, and setting based, on the detection result, a potential corresponding to the identifying voltage.

Electronic device, detection circuit and voltage control method

A detection circuit that reduces circuit scale. A plurality of current amplifiers respectively generate a plurality of detection signals corresponding to current flowing to a plurality of resistors. An error amplifier coupled to the plurality of current amplifiers compares the plurality of detection signals with a plurality of reference signals, respectively, to generate an error signal based on the comparison.

Detection circuit

A detection circuit for generating a control signal for controlling output voltage of an AC adapter. The detection circuit for an electronic device receives power information from an external power supply via a cable to generate the control signal that controls DC input voltage output from the external power supply. In the detection circuit, a correction voltage generation circuit generates a correction voltage in correspondence with the parasitic resistance of the cable. A power information correction circuit corrects the power information provided from the external power supply via the cable with the correction voltage to generate corrected power information. A detection signal generation circuit calculates the total power amount of the electronic device and generates a power detection signal corresponding to the total power amount. The control signal generation circuit generates the control signal based on the corrected power information and the power detection signal.

An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period Hwhich is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC, thereby changing the output voltage VO() only by the offset voltage VO() by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data Dto Dconducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Operational amplifier, line driver, and liquid crystal display device

A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.

Method and circuit for controlling DC-DC converter

A power supply system including an external power supply unit generating direct-current output voltage and an electronic device connected to the external power supply unit and operable on the output voltage of the external power supply unit. The external power supply unit includes a voltage control circuit receiving control current and controlling the output voltage of the external power supply unit in accordance with the control current. The voltage control circuit controls the output voltage of the external power supply unit to be equal to the minimum voltage possible for the external power supply unit to generate when the control current is minimum.

Power supply system and method for controlling output voltage

A DC-DC converter that suppresses increase in area and obtains high conversion efficiency irrespective of the output current. A controller controls a first output transistor and a second output transistor in a PWM operation mode or a linear operation mode based on output voltage of the DC-DC converter. The controller operates the DC-DC converter as a switching regulator that activates and inactivates the first output transistor and the second output transistor in a complementary manner during the PWM operation mode. The controller operates the DC-DC converter as a linear regulator that inactivates the second output transistor and controls the ON-resistance value of the first output transistor to perform linear operation with the first output transistor during the linear operation mode.

Controller for DC-DC converter and method for controlling DC-DC converter

A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Semiconductor device and liquid crystal panel driver device

Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Semiconductor integrated circuit for driving liquid crystal panel

An image processing circuit for a color image sensor, comprising a color sensitivity correction circuit which adds/subtracts a predetermined offset to/from pixel signals being output by amplifying photoelectric conversion signals of pixels, which have photoelectric conversion element and are arranged in column and row directions, for each column, and multiplies the result by a predetermined gain, wherein the predetermined offset includes a first offset, which is set according to each color, and a second offset, which is set according to a plurality of columns. According to the present invention, the offset of the color sensitivity correction circuit includes a first offset, which is set according to each color, and a second offset, which is set according to a plurality of columns, therefore, periodic moir&#xe9; in the vertical direction, which is caused by the column output circuit and the output signal supply circuit for each column, can be suppressed, and image quality can be improved.

Image processing circuit providing improved image quality

A differential amplifying circuitincludes a current mirror circuit having first and second current ends to which drains of MOS transistors Mand Mare respectively connected, and a pair of differential MOS transistors Mand Mhaving gates between which a switch SWis connected. A reference potential Vref is applied to the gate of the MOS transistors M. A switch SWis connected between the output VO of an output buffer circuitand the gate of a MOS transistor M, and a switch SWis connected between the output VO and the gate of the MOS transistor M. During the offset-cancel preparation period, the switches SWand SWare on and the switch SWis off. Next, the switches SWto SWare turned over, consequently outputting offset-canceled potential VO.

Offset cancel circuit of voltage follower equipped with operational amplifier

The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiodea source follower amplifierfor converting an electric charge of the photodiodeinto a voltage and amplifying it to output image data, and a horizontal selection transistorfor outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuithas a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.

X-Y address type solid-state image pickup device with an image averaging circuit disposed in the noise cancel circuit

A CMOS image sensor that reduces kTC noise in a wide band. A pixel circuit corresponding to one pixel includes a photoelectric conversion element for carrying out the photoelectric conversion of incident light, a reset transistor for resetting a cathode of the photoelectric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion element to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction. A voltage control circuit controls the potential of a gate of the reset transistor during a period when the photoelectric conversion element is reset to change ON-state resistance of the reset transistor. By doing so, a cutoff frequency for a low-pass filter formed in the pixel circuit by ON-state resistance of the reset transistor and parasitic capacitance produced at the cathode on the photoelectric conversion element will be controlled.

Growing community of inventors

Kawasaki, Japan

Masatoshi Kokubun