Hitachi, Ltd.

Masatoshi Kawashima

Hideki Hayashi

Akira Yamagiwa

Koichi Sugimoto

Toshihiro Okabe

Koki Tsutsumida

Tsutomu Sato

Kiyokazu Arai

Makoto Takechi

Hisakazu Date

Toyohito Ikeya

Kenichi Tada

Hiroshi Odani

A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit.

Semiconductor device

A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.

Semiconductor integrated circuit device and method of design of semiconductor integrated circuit device

A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width. When the electrical power requirement of a function circuit is significantly larger than that of another function circuit, the wire width may be increased in the vicinity of the one function circuit. When the function circuits include a large-scale function block, a wire width around a region of the integrated circuit chip in which the large-scale block is to be disposed may be selected which results in a wire area equal to the wire area of the power supply wire that would occupy the particular region for usual function circuits.

Method of wiring for power supply to large-scale integrated circuit

A LSI circuit having at least one combinational circuit and a latch coupled to the input side of the combinational circuit. The latch includes a switch for inhibiting the latching of either test data for testing the combinational circuit or data for a normal operation.

LSI logic circuit

A semiconductor integrated circuit device which includes input and output buffers having a high versatility of design is disclosed. Each buffer provided in correspondence with a bonding pad is made usable for either the input buffer or the output buffer in accordance with a wiring pattern to be formed therein. With this arrangement, it is possible to use the same circuit elements for both the input buffer and the output buffer. Thus, circuit elements to be exclusively used for inputting and outputting respectively need not be separately formed, and the area occupied by the buffers is reduced to that extent, to realize an increase in the number of pins or a reduction in the size of a chip. In addition, since one buffer can be set for either inputting or outputting, enhancement in the versatility of the design of the pins or the chip is achieved.

Growing community of inventors

Hamura, Japan

Masatoshi Kawashima