Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Other

Mitsubishi Electric Engineering Company, Limited

Masatoshi Ishikawa

Tsukasa Ooishi

Hideto Hidaka

Hiroaki Tanizaki

Shigeki Tomishima

Takaharu Tsuji

Hiroshi Kato

Mitsutaka Niiro

Masanao Maruta

Katsumi Dosaka

Jun Ohtani

An MTJ memory cell has an access transistor which turns on in response to activation of a corresponding word line and a tunneling magneto-resistance element which has an electric resistance changing in accordance with stored data. The access transistor has a source connected to a source line for supplying a ground voltage. To restrict an off leakage current in a non-selected access transistor, each access transistor is configured with a MOS transistor having a threshold voltage that is larger than that of another MOS transistor formed on the same chip.

Thin film magnetic memory device permitting high precision data read

An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Semiconductor integrated circuit device with internal power supply potential generation circuit

A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Semiconductor device with reduced current consumption in standby state

An access transistor ATR in an MTJ memory cell, which is one of transistors connected to a read current path, is constituted with a surface-channel, field-effect transistor. The surface-channel, field-effect transistor has a channel resistance lower than a channel-embedded, field-effect transistor, and can reduce an RC load in the read current path. Accordingly, data can be read with a high speed.

Thin film magnetic memory device suppressing resistance of transistors present in current path

An access transistor in an MTJ memory cell, which is one of transistors connected to a read current path, is fabricated with a semiconductor layer formed on an insulating film on a semiconductor substrate SUB, and includes impurity regions, a gate region and a body region. That is, the access transistor is fabricated with an SOI (Silicon On Insulator) structure in order to reduce an off-leak current.

Thin film magnetic memory device with magnetic tunnel junction

A memory array is provided with first MTJ memory cells arranged in alternate rows and second MTJ memory cells arranged in other alternate rows and each having a layout inverted in a Y direction with respect to the first MTJ memory cell. In each memory cell column, first and second transistor gate interconnections are arranged in the Y direction. In the first MTJ memory cell, a gate of a transistor provided as an access element is connected to the first transistor gate interconnection. In the second MTJ memory cell, a gate of a transistor provided as an access element is connected to the second transistor gate interconnection.

Thin film magnetic memory device selecting access to a memory cell by a transistor of a small gate capacitance

A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation

A tunneling magneto-resistance element forming an MTJ memory cell is connected between a bit line and a strap. In each memory cell column, the strap is shared by the plurality of tunneling magneto-resistance elements in the same row block. The access transistor is connected between strap and ground voltage, and is turned on/off in response to a corresponding word line. Storage data is read from the selected memory cell based on a comparison between results of data reading effected on a memory cell group coupled to the same strap before and after application of a predetermined magnetic field to the selected memory cell.

Thin film magnetic memory device having an access element shared by a plurality of memory cells

In a memory cell array of an MRAM, a reference memory cell holding a reference value can generate accurate reference current of an intermediate value of data by uniformly supplying reference current to two sense amplifiers using two cells of a cell holding &ldquo;H&rdquo; data and a cell holding &ldquo;L&rdquo; data. Each bit line is connected to a data-storing memory cell and to the reference memory cell. When the data-storing memory cell connected to a bit line is accessed, the reference memory cell is accessed on the adjacent bit line. Only one row of reference memory cells is provided, reducing the chip area. Therefore, a non-volatile memory device that can reduce the area of a reference cell occupied on a chip while generating accurate reference current for determination can be provided.

Non-volatile memory device capable of generating accurate reference current for determination

A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

Thin film magnetic memory device sharing an access element by a plurality of memory cells

A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode

For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.

Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system

A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Semiconductor device having MOS transistor for coupling two signal lines

In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

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Hyogo, Japan

Masatoshi Ishikawa