Fujitsu Corporation

International Business Machines Corporation

Canon Kabushiki Kaisha

Samsung Electronics Co., Ltd.

Masatoshi Ishii

Kohji Hosokawa

John David Baniecki

Kazuaki Kurihara

Atsuya Okazaki

Takeo Yasuda

Junka Okazawa

Kazunori Yamanaka

Yutaka Nakamura

Masayuki Kato

Takayuki Osogami

Teru Nakanishi

Motoyuki Nishizawa

Chung H Lam

Yasuo Yamagishi

Nobuyuki Ohba

Tsuyoshi Aoki

Akio Sugama

Scott C Lewis

Hisatada Miyatake

Akihiko Akasegawa

SangBum Kim

Gen Yamada

Masao Kondo

Takeshi Shioga

Geoffrey W Burr

Yoshiyasu Nakashima

Pritish Narayanan

Koji Tsukamoto

Megumi Ito

Shinya Sasaki

Keisuke Sato

Akiyo Iwashina

Paul Michael Solomon

Martin Michael Frank

Masataka Mizukoshi

Kishio Yokouchi

Takashi Hanamoto

Jin Ping Han

Hiroshi Nakao

Timothy Phung

Kazutoshi Hayashi

Aakash Pushp

Yasutoshi Kotaka

Michihiro Aoyama

Masayuki Katoh

An image processing apparatus includes an image acquisition unit configured to acquire a first thumbnail image having a first angle of view recorded in an image file, an image generation unit configured to generate a second thumbnail image having a second angle of view different from the first angle of view, an image setting unit configured to set a thumbnail image to be displayed in a thumbnail display area depending on whether a cursor operated by a user is located in the thumbnail display area on a screen, and a display unit configured to display a thumbnail image set by the image setting unit in the thumbnail display area on the screen, wherein, in a case where a cursor is located in the thumbnail display area on the screen, the image setting unit sets the second thumbnail image as a thumbnail image to be displayed in the thumbnail display area.

Image processing apparatus, image processing method, and storage medium

An image processing apparatus is configured to determine presence or absence of print abnormality in a target image by comparing a reference image or reference images, each of which is a print result to be a reference, and the target image, which is a print result to be an inspection target. The image processing apparatus includes a setting unit configured to set an inspection condition for a printed product, and a comparison unit configured to compare the reference image or reference images and the target image using a number of the reference images set based on the inspection condition.

Image processing apparatus, image processing method, and storage medium for determining presence or absence of print abnormality

A computer-implemented method, according to one embodiment, includes: causing a multi-bit input to be split into two or more chunks, where each of the two or more chunks include at least one individual bit. Each of the two or more chunks are also converted into a respective pulse width modulated signal, and a partial result is generated in digital form for each of the respective pulse width modulated signals. Each of the partial results are scaled by a respective significance factor corresponding to each of the two or more chunks, and the scaled partial results are also accumulated.

Split pulse width modulation to reduce crossbar array integration time

A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N:1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.

Bias scheme for single-device synaptic element

There is provided with an image-processing apparatus for indicating a range, which is displayed by a device or a system comprising a display area for displaying an image, within an input image. A first obtaining unit obtains information that represents a display form of the device or the system comprising the display area. A second obtaining unit obtains input image data representing the input image. An identification unit identifies the range, which is displayed in the display area, within the input image based on the input image data and the information. An output unit outputs information that represents the identified range. A shape of the identified range depends on the display area that corresponds to at least a curved screen or a plurality of flat screens.

Image-processing apparatus for indicating a range within an input image, processing method, and medium

In an image processing apparatus, a condition for detecting a print position deviation on a print medium in a printed material is set. Based on the condition, data obtained by reading the print medium for the print position deviation is inspected. In the condition, in a case where a width of the print medium is larger than a readable width for reading the print medium, a settable range is small relative to a case where the width of the print medium is smaller than the readable width.

Image processing apparatus, image processing method, and recording medium

There is provided with an image processing apparatus that generates a display image to be displayed in a display system including a display area. An obtaining unit obtains one input image acquired through shooting by one image capturing apparatus. A generating unit generates the display image from the input image on the basis of a correspondence between a first projection plane corresponding to the input image and a second projection plane corresponding to the display area.

Image processing apparatus, display system, image processing method, and medium

A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Selective application of multiple pulse durations to crossbar arrays

A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

Neuromorphic chip for updating precise synaptic weight values

An image processing apparatus is described comprising a first acquisition unit configured to acquire image data from an image capturing apparatus and a second acquisition unit configured to acquire display installation information indicating a configuration of one or more display screens in a display installation to be simulated. A generation unit is provided to generate, based on the display installation information and the acquired image data, a simulation image that simulates display of the image on the display installation. A display control unit is provided to display the simulation image on a display device.

A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.

Synapse memory cell driver

A spiking neural network device including a spiking neural network circuit including a crossbar array of plural synapses; plural axons connected with the spiking neural network circuit, the plural axons receiving input of a spike signal; and plural Poisson spike generators respectively provided for the plural axons. Each Poisson spike generator can be set whether or not to emit the spike signal based on an input signal to be processed, and each Poisson spike generator can, be set to emit the spike signal being configured to generate a Poisson spike train different from each other. and supply the Poisson spike train to a corresponding one of the plural axons.

On-chip Poisson spike generation

Image processing apparatus and image processing method for simulating a display installation

A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Monitoring potential of neuron circuits

Growing community of inventors

Kawasaki, Japan

Masatoshi Ishii