Fujikura Limited

Texas Instruments Japan Limited

Other

Masatoshi Inaba

Masahiro Kaizu

Akihito Kurosaka

Takanao Suzuki

Tadanori Ominato

Mutsumi Masumoto

Kenji Masumoto

Nobuyuki Sadakata

Masakazu Sato

Yoshiharu Unami

Nobuki Ueta

Kanako Nakajima

Hirohito Watanabe

Hiroshi Miyata

Yoshio Nakao

A component-embedded substrate includes: a plurality of insulating layers each including a wiring pattern formed on one surface; an embedded component including a connection terminal; and a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. The plurality of insulating layers is laminated on the connection terminal. Each of the plurality of vias is composed of a via hole formed in the respective insulating layer of the plurality of the insulating layers and a conductive material provided in the via hole. One of the plurality of vias is a connection via directly connected to the connection terminal. Another of the plurality of vias is a first adjacent via adjacent to the connection via in the lamination direction. The first adjacent via is connected to the wiring pattern formed on a surface of a top insulating layer.

Component-embedded substrate

A component-embedded substrate includes: insulating layers each including a wiring pattern; an embedded component including a connection terminal; a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. Each of the vias is composed of a via hole in the insulating layer and a conductive material in the via hole. One of the vias is a connection via connected to the connection terminal, and another of the vias is an adjacent via adjacent to the connection via in the lamination direction. The connection via and adjacent via overlap in a plan view. S1/A1&#x2264;0.61 and S1/A2&#x2264;0.61 are satisfied, where A1 is an average cross-sectional area of the connection via, A2 is an average cross-sectional area of the adjacent via, and S1 is an overlapping area of the connection via and adjacent via in the plan view.

A method of manufacturing a printed circuit board includes: forming a copper layer of an interconnection pattern on a base film; laminating a cover lay on the base film so as to expose a part of the copper layer from the cover lay and cover the copper layer by the cover lay; mechanically polishing at least the exposed portion of the copper layer; and performing a plating process on the exposed portion of the copper layer so as to form a plated layer on the copper layer, and the angles &#x3b1;and &#x3b1;between the polishing direction of the exposed portion of the copper layer and the bending lines Cand Csatisfy the following formula (1):30&#xb0;&#x2266;&#x3b1;and &#x3b1;&#x2266;150&#xb0;&#x2003;&#x2003;(1).

Method of manufacturing printed circuit board and printed circuit board

A printed circuit board includes a flexible insulated substrate with a first surface and a second surface at both sides respectively, a wiring layer on the first surface, a reinforcement plate on a part of the second surface and an auxiliary layer between the second surface and the reinforcement plate. A reinforcement edge side of the reinforcement plate is located at the outside of an auxiliary edge side of the auxiliary layer.

Printed circuit board and manufacturing method thereof

An insulating layer () having an opening portion () at a position conformable to an electrode pad () is formed. Next, a resin projection portion () is formed on the insulating layer (). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (), the resin projection portion () and the region sandwiched therebetween. A Cu plating layer () is formed by electrolytic copper plating, using the resist film as a mask.

Method for producing a semiconductor package, with a rerouted electrode formed on a resin projection portion

Semiconductor package, semiconductor device and electronic device

An insulating layer ( ) having an opening portion ( ) at a position conformable to an electrode pad ( ) is formed. Next, a resin projection portion ( ) is formed on the insulating layer ( ). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion ( ), the resin projection portion ( ) and the region sandwiched therebetween. A Cu plating layer ( ) is formed by electrolytic copper plating, using the resist film as a mask.

Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package

An insulating layer ( ) is formed on a Si wafer ( ). An opening portion is made in this insulating layer ( ), and subsequently a rerouting layer ( ) is formed. Next, a resin layer ( ) is formed on the rerouting layer ( ). The resin layer ( ) is then cured so that the rerouting layer ( ) and a Cu foil ( ) are bonded to each other through the resin layer ( ). Thereafter, a ring-like opening portion ( ) is made in the resin layer ( ), and a Cu plating layer ( ) is formed inside this opening portion ( ).

Growing community of inventors

Tokyo, Japan

Masatoshi Inaba