Fujitsu Corporation

Masatoshi Haraguchi

Hideki Okawara

Yuji Watanabe

Masaki Arai

Masakazu Hayashi

KohIchiro Hotta

Tadashi Nakahira

Masanori Yamanaka

Masanori Kira

Shun Kamatsuka

Kensuke Watanabe

Yasunobu Tanimura

Kotaro Taki

A compiler program causes a computer to execute optimization processing for an optimization target program. The optimization target program includes a loop including a vector store instruction and a vector load instruction for an array variable. The optimization processing includes (1) unrolling the vector store instruction and the vector load instruction in the loop by an unrolling number of times to generate a plurality of unrolled vector store instructions and a plurality of unrolled vector load instructions, and (2) scheduling to move an unrolled vector load instruction among the plurality of unrolled vector load instructions, which is located after a first unrolled vector store instruction that is located at first among the plurality of unrolled vector load instructions, before the first unrolled vector store instruction.

Compiler program, compiling method, information processing device

A method of compiling a first program to output a second program, the method includes: determining a number of arithmetic units to be operated during execution of the second program for each of a plurality of sections in the first program; and creating the second program by adding an instruction to specify the number of arithmetic units to be operated to each of the plurality of sections based on the determining.

Method and apparatus for compiling a program for execution by a plurality of processing units

A processor includes an instruction executing unit which executes a memory access instruction, a cache memory unit disposed between a main memory which stores data related to the memory access instruction and the instruction executing unit, a control information retaining unit which retains control information related to a prefetch issued to the cache memory unit, an address information retaining unit which retains address information based on the memory access instruction executed in the past, and a control unit which generates and issues a hardware prefetch request. The control unit compares address information retained in the address information retaining unit and an access address in the memory access instruction executed, and generates and issues based on a comparison result a hardware prefetch request to the cache memory unit according to the control information of the control information retaining unit specified by specifying information added to the memory access instruction.

Processor and control method of processor

In a compiler apparatus, a memory unit stores a first code including a loop having a first arithmetic expression including a first variable that refers to a result of K iterations previous calculation. A transformation unit develops the first arithmetic expression into a second arithmetic expression not including the first variable, using a second variable that refers to a result of K+1 iterations or more previous calculation, compares an execution time for executing the loop on the basis of the first arithmetic expression with an execution time for executing the loop in which the calculations of Jth and J+Kth iterations of the loop are executed in parallel on the basis of the second arithmetic expression, and decides based on the comparison result whether to transform the first code into a second code including a parallel processing instruction for executing the Jth and J+Kth iterations in parallel.

Compiler method and compiler apparatus for optimizing a code by transforming a code to another code including a parallel processing instruction

An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address requested by a hardware prefetch request issuing section for memory access and address information held in an address information holding section, wherein when the control section causes the address information holding section to hold address information or address information in the address information holding section is updated, overwrite processing on the address information is inhibited for a predetermined time.

Information processing unit, program, and instruction sequence generation method

In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Software development tool program

An apparatus for facilitating optimization processing in a compiler includes a language-specific-rule table which stores one or more predetermined rules which are specified for one or more programming languages; an analyzing unit which analyzes a program code which includes one or more instructions, and is described in one of the one or more programming languages, based on the one or more predetermined rules, to obtain an analysis result; and an embedding unit which embeds the analysis result in the program code.

Method and apparatus for analyzing program based on rules of programming language before optimization in compiler

In order to generate optimum codes for array descriptions having a new language specification, an optimization control apparatus or method for array description executes a function of determining a scope of executing optimization for the array descriptions on the basis of an optimization level determined in advance, the dimension number of an array of the array descriptions, and the array number of each dimension; a function of extracting information representing the respective forms of the array descriptions within the scope of executing the optimization; a function of detecting a common expression for each array description and recognizing information common to each array description; and a function of executing a loop merge determination process as to whether or not a loop merge for converting each array description to an optimum loop is to be carried out, for each array description whose form is defined during the generation of the optimum codes.

Optimization control apparatus and optimization control method for array

The entire space of a loop is analyzed for dependencies between target array elements so that dependency ID's are assigned to the target array elements. Optimization is carried out on the basis of the dependency ID's. Dependency ID's covering dependency for an arbitrary turn of the loop are reassigned to the target array elements that have been subjected to optimization, whereupon a further optimization is carried out. An examination for identifying overlappings is carried out on the basis of the dependency ID assigned to the target array elements so that instruction scheduling is carried out.

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Fuji, Japan

Masatoshi Haraguchi