Mitsubishi Denki Kabushiki Kaisha

Masatoshi Aikawa

Tsunenori Umeki

Akira Yamada

Hiromasa Nakagawa

A novel method for making complementary semiconductor IC devices is described. The method includes the steps of: preparing a N-type semiconductor substrate; preparing a first mask for forming a P-well in the N-type substrate; forming the P-well in the N-type substrate using the first mask; preparing a second mask for forming a first P-type diffusion regions in the substrate and in the P-well; preparing a third mask for forming N-type diffusion regions in the substrate and in the P-well; preparing a fourth mask for forming a second P-type diffusion regions in the unoccupied areas of the N-type substrate and the P-well by carrying out reversing, AND and OR processing of the first, second and third masks, and forming the P-type diffusion regions in the prescribed areas of the substrate and the P-well by placing the fourth mask on the substrate.

Method of fabricating complementary semiconductor integrated circuits

A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.

Growing community of inventors

Hyogo, Japan

Masatoshi Aikawa