Fujitsu Corporation

Masatoshi Aihara

Koji Hosoe

Akio Tokoyoda

Makoto Suga

Yuta Toyoda

Koichiro Takayama

The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

Arithmetic processing device storing diagnostic results in parallel with diagnosing, information processing apparatus and control method of arithmetic processing device

An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.

Information processing apparatus, memory controller, and memory control method

An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.

Arithmetic processing unit, and method of controlling arithmetic processing unit

A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

Memory controller, information processing apparatus, and method of controlling memory controller

An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

Arithmetic processing device, information processing device, and control method of arithmetic processing device

The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.

Information processing apparatus and control method of information processing apparatus

A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.

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Hiratsuka, Japan

Masatoshi Aihara