Shinko Electric Industries Co., Ltd.

Fujitsu Corporation

Kabushiki Kaisha Tiyoda Seisakusho

Kabushiki Kaisha Tiyoda Sisakusho

Masato Tanaka

Akio Rokugawa

Noriyoshi Shimizu

Akihiko Tateiwa

Yoshihiro Nakata

Yasushi Kobayashi

Sadahiro Kishii

Mitsuharu Shimizu

Tsuyoshi Kanki

Wataru Kaneda

Hitoshi Sakaguchi

Tadayoshi Ichikawa

Katsuya Fukase

Shigetsugu Muramatsu

Yasuyoshi Horikawa

Yoshihiro Ihara

Toshinori Koyama

Tetsuya Koyama

Masahiro Kyozuka

Shoji Watanabe

Hiromu Arisaka

Katsumi Yamazaki

Kenji Mochizuki

Toshiyuki Murakami

A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers formed from a thermosetting insulative resin respectively including first and second reinforcement materials, and a via wire formed in the first insulation layer. The second wiring structure includes a third insulation layer formed on an upper surface of the first insulation layer and an upper end surface of the via wire, and a wiring layer extended through the third insulation layer and electrically connected to the via wire. The outermost insulation layer, the main component of which is a photosensitive resin, is stacked on a lower surface of the second insulation layer. The second wiring structure has a higher wiring density than the first wiring structure. The first reinforcement material is partially exposed on the upper surface of the first insulation layer.

Wiring substrate and semiconductor device

A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.

A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V/Vis from 0.8 to 1.5, where Vrepresents the volume of the wiring layers forming the entire second wiring structure, and Vrepresents the volume of the bottom wiring layer in the first wiring structure.

Wiring substrate, semiconductor device, and method of manufacturing wiring substrate

A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.

Wiring board

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Semiconductor package and method for manufacturing semiconductor package

A semiconductor device includes a semiconductor chip, a core substrate, first and second insulating layers, and first and second wiring layers. Adhesiveness of the insulating layer to a metal is higher than adhesiveness of the core substrate to the metal. A through hole extends through the insulating layer in the thickness direction. A through via covers the hole wall surface of the through hole, extends in the thickness direction traversing the insulating layer, and electrically connects the first and second wiring layers.

Semiconductor package, semiconductor device, and method for manufacturing semiconductor package

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

Semiconductor package including a metal plate, semiconductor chip, and wiring structure, semiconductor apparatus and method for manufacturing semiconductor package

A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Semiconductor device and its manufacture method

A socket detachably connects a connecting item to a substrate via connecting terminals. The socket includes a support member with first and second surfaces to fix the connecting terminals, and penetrating holes formed in the support member. Each connecting terminal includes first and second connecting parts formed on opposite ends thereof. Each connecting terminal is inserted into a corresponding penetrating hole in a state in which the first connecting part is fixed to the first surface and the second connecting part projects from the second surface of the support member.

Socket and method of fabricating the same

A socket includes: a circuit board; a plurality of connection terminals disposed on the circuit board; a plurality of contacts each fixed to a corresponding one of the connection terminals, wherein each of the contacts is formed of a conductive elastic member, each of the contacts comprising: a tail portion fixed to the corresponding connection terminal; an extending portion connected to the tail portion and extending in a direction substantially parallel with a surface of the circuit board; a rise portion connected to the extending portion and extending in a direction substantially perpendicular to the surface of the circuit board; and a tip portion connected to the rise portion.

Socket and semiconductor device including socket and semiconductor package

A multilayer interconnection board is disclosed that allows reliable electrical connection between an interconnection having a large width and a large area and a via provided in a via hole formed by pressing a tool against resin. A projecting portion for electrical connection is formed integrally with the insulating member and in a second interconnection groove having a width and an area greater than those of a first interconnection groove. While a first interconnection is being deposited in the first interconnection groove and a second interconnection is being deposited in the second interconnection groove, the projecting portion is formed in the second interconnection groove and a metal plating film is provided on the projecting portion at the same time, so as to electrically connect the second interconnection with the via.

Multilayer interconnection board and production method thereof

A metal-core-type multi-layer lead frame adapted to be used for a semiconductor device includes a metal core plate on which a semiconductor chip is to be mounted. A plurality of signal lines are formed on the metal core plate. A metal plane, such as a power supply plane or a ground plane, is laminated on the signal lines, through an insulating layer, so that an outer peripheral edge of said metal core plate is uncovered to expose the outer portion of the respective signal lines. A lead frame body has a plurality of leads which are electrically connected to the respective signal lines at the outer peripheral edge of the metal core plate.

Multi-layer lead frame using a metal-core substrate

A lead frame to be used for a semiconductor device, comprising: a heat sink having a peripheral area and a central projected land on which a semiconductor chip is to be mounted. The heat sink has a relatively good heat radiating characteristic. A plurality of inner leads are provided, each having an inner end superimposed on the peripheral area of the heat sink by an insulating material. A semiconductor chip has a chip surface on which a junction pattern is arranged, and is mounted on the projected land of the heat sink by an insulating adhesive so that the chip surface faces the projected land. TAB leads are provided for electrically connecting the semiconductor chip to the inner leads, and a sealing resin hermetically seals at least the semiconductor chip.

Growing community of inventors

Nagano, Japan

Masato Tanaka