Toyota Jidosha Kabushiki Kaisha

Renesas Electronics Corporation

Masato Taki

Masahiko Kashimura

Yoshihiro Nagai

Kazushi Yamanaka

Masakazu Amanai

Norihiro Honda

Masayuki Furumiya

Shinichi Uchida

Yoshiyuki Sato

Jun Morimoto

Kozo Kato

Masayasu Ishiko

Hidetoshi Morishita

Hideki Tojima

Takashi Iwadare

Kiyoharu Hayakawa

Masahiro Kawakami

Makoto Eguchi

Hiroshi Sakakibara

A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.

Semiconductor device

Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least &#xbd; as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage.

Booster circuit

A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.

Nonvolatile semiconductor memory device

A diodecomprises an SOI substrate in which are stacked a semiconductor substrate, an insulator film, and a semiconductor layer. A bottom semiconductor region, an intermediate semiconductor region, and a surface semiconductor regionare formed in the semiconductor layer. The bottom semiconductor regionincludes a high concentration of n-type impurity. The intermediate semiconductor regionincludes a low concentration of n-type impurity. The surface semiconductor regionincludes p-type impurity.

Lateral SOI semiconductor devices and manufacturing method thereof

A semiconductor apparatus () comprises a low potential reference circuit region () and a high potential reference circuit region (), and the high potential reference circuit region () is surrounded by a high withstand voltage separating region (). By a trench () formed in the outer periphery of the high withstand voltage separating region (), the low potential reference circuit region () and high potential reference circuit region () are separated from each other. Further, the trench () is filled up with an insulating material, and insulates the low potential reference circuit region () and high potential reference circuit region (). The high withstand voltage separating region () is partitioned by the trench (), high withstand voltage NMOS () or high withstand voltage PMOS () is provided in the partitioned position.

Semiconductor apparatus

Growing community of inventors

Miyoshi, Japan

Masato Taki