Fujitsu Corporation

Masato Susuki

Hiroshi Nakadai

A semiconductor integrated circuit includes a plurality of areas, each of which generates phase clocks in accordance with an external clock and control signals and performs a predetermined process assigned to each of the phase clocks. The semiconductor integrated circuit includes a control signal distributing unit that adjusts a timing at which the control signal is turned ON or OFF for each of the areas and distributes the adjusted control signals to the plurality of areas so that the plurality of areas do not perform a same process at a same timing.

Semiconductor integrated circuit and control signal distribution method

For the purpose of providing an inexpensive memory from which test results can be certainly read out, a semiconductor device having a BIST circuit (built-in self test circuit) includes a RAM for use in processing to be tested incorporated in a data processing system, a built-in self test circuit making a built-in self test on the RAM for use in processing, and a RAM for tester storing test results of the RAM for use in processing obtained by the built-in self test circuit so that the test results can be read out by an external tester, wherein a RAM having a data read-out margin greater than a data read-out margin of the RAM for use in processing is used as the RAM for tester.

Semiconductor device and testing apparatus for semiconductor device

This semiconductor device is equipped with a surplus address detection circuit with a small area and the circuit can be used commonly for various maximum word sizes. The semiconductor comprises a memory for an intermediate word size having X rows or columns, where X is between Nth power of 2 and (N-1)th power of 2, and N is a natural number, an address decoder that decodes address signals addressing rows or columns of the memory for an intermediate word size to be accessed, and a surplus address detection circuit that detects accesses to surplus addresses larger than number X. The address decoder comprises plural pre-decoders that decode address signals classified into plural groups and a post-decoder that generates a selection signal that selects a row or column to be accessed by the combination of outputs of the plural pre-decoders. The surplus address detection circuit detects accesses to surplus addresses larger than number X by the outputs of the plural pre-decoders, and the number of the input signal lines of the surplus address detection circuit is smaller than that of the outputs of the plural pre-decoders, and only a part of the outputs of the plural pre-decoders is supplied to the surplus address detection circuit.

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Kawasaki, Japan

Masato Susuki