Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Masato Suga

Shigetoshi Wakayama

Jusuke Ogura

Satoshi Nakai

Hiroyuki Kato

Mutsuaki Kai

Matsuaki Kai

A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Method of manufacturing semiconductor integrated circuit device

A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

Semiconductor device having a guard ring

A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to the first minimum wire width, formed on a second wiring layer which differs from the first wiring layer and extending in a diagonal direction in relation to the orthogonal wire; and a via having a size which is no greater than the first or second wire width, formed at point at which the orthogonal wire and diagonal wire overlap so as to connect the orthogonal wire and diagonal wire, wherein one of the diagonal wire and orthogonal wire includes an enlarged wire width region in the position at which the via is formed, the wire width of the enlarged wire width region being enlarged beyond the first or second minimum wire width.

Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor

A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.

Growing community of inventors

Kawasaki, Japan

Masato Suga