Nec Corporation

Nec Electronics Corporation

Masato Sakao

Shuichi Ohya

Yoshihiro Takaishi

Takeshi Akimoto

Seiichi Shishiguchi

Shizuo Oguro

Kiyonori Kajiyana

A semiconductor device of the present invention comprises a capacitor portion composed of a lower electrode, a capacitor insulator film, and an upper electrode sequentially stacked on an inter-layer insulator film on a semiconductor substrate; and a charging protection portion sharing the capacitor insulator film and the upper electrode. The lower electrode is electrically connected through a first contact plug provided in the inter-layer insulator film finally to a first diffused layer formed in the semiconductor substrate surface, the capacitor insulator film of the charging protection portion is adhered to a second contact plug provided in the inter-layer insulator film, the contact plug is electrically connected finally to a second diffused layer formed in the semiconductor substrate surface, and the lower electrode is made of a first conductive material and the first and second contact plugs are made of a second conductive material different from the first conductive material.

Semiconductor device having stacked capacitor and protection element

A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric, an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening. The lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate. A conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.

Semiconductor device having capacitor and method thereof

There is provided a method of fabricating a semiconductor memory device including a memory cell having transistor and a capacitor, and a cylindrical accumulation electrode, the method including the steps of (a) forming a first insulating film on a lower interlayer insulating film, (b) forming at least one hole through the first insulating film so that the hole reaches the lower interlayer insulating film, (c) forming a polysilicon layer in the hole so that an upper surface of the polysilicon layer is located lower than an upper surface of the first insulating film, (d) covering the first insulating film and the polysilicon layer with a second insulating film, (e) etching back the second insulating film so that the second insulating film remains only on a sidewall of the first insulating film, and (f) etching the polysilicon layer with the second insulating film being used as a mask so that the polysilicon layer has a thickness different from a thickness of the first insulating film after the polysilicon layer has been etched. The method makes it possible to independently determine thicknesses of a sidewall and a bottom of a cylindrical accumulation electrode, and hence, design the bottom to have a greater thickness than a thickness of the sidewall. This ensures less risk of fall-down of the sidewall of the cylindrical accumulation electrode, higher structural stability, and higher capacity of the cylindrical accumulation electrode.

Semiconductor memory device and method of fabricating the same

A plurality of charge storage electrodes are formed on an interlayer insulating film which is formed on a silicon substrate. A plurality of insulating members which surround periphery of the charge storage electrodes and which are separated from each other are formed. A capacitance insulating film is so formed as to cover the plurality of charge storage electrodes and the plurality of insulating members. A plate electrode is formed on the capacitance insulating film. The insulating members are formed of a silicon nitride film which has a function as an etching stopper for protecting the interlayer insulating film.

Semiconductor memory device and manufacturing method of the same

A pair of semiconductor memory cells comprises active regions having rectangular shapes, arranged in uniform intervals in plan view, said active regions constituting channel regions and source/drain regions of switching transistors; word lines arranged so as to be perpendicular to the active regions; and an extraction electrode connected to a bit line through bit a line contact formed in connection to the active regions constituting the pair of switching transistors.

Semiconductor memory cell

A miniaturized contact in a semiconductor substrate is provided. The contact comprises a diffused layer formed at a surface of the substrate, an interlayer film for covering the diffused layer, a plurality of lower interconnections buried within the interlayer film, an upper interconnection disposed on the interlayer film and a contact hole passing through the interlayer film for connecting the diffused layer with the upper interconnection. The contact hole has an aperture diameter equivalent to a space interval between the lower interconnections. The contact further comprises a first buried conductor disposed only from the bottom of the contact hole to a height lower than that of the lower interconnections, a side-wall insulator disposed on a side-wall of the contact hole above the first buried conductor, and a second buried conductor disposed on the first buried conductor within the contact hole.

Miniaturized contact in semiconductor substrate and method for forming the same

A semiconductor device which has a MOS transistor having a gate electrode composed of a first conductive film formed on a silicon substrate; a resistance element composed of a second conductive film formed on a field insulating film formed on the silicon substrate; and a plurality of conductive film patterns formed in parallel at predetermined intervals on the surface of the field insulating film, wherein the plurality of conductive film patterns are of the first conductive film type connected with a predetermined potential, and the top surface and side of each of the plurality of conductive film patterns are covered with an insulating film; wherein the resistance element is formed reciprocative-crossing several times in the orthogonal direction to the plurality of conductive film patterns through the insulating film on the plurality of conductive film patterns.

Semiconductor device having a resistance element with a reduced area

A storage capacitor with a double cylindrical storage electrode is incorporated in a semiconductor dynamic random access memory cell, the double cylindrical storage electrode is electrically connected through a node contact hole to a source region of a switching transistor, the double cylindrical storage electrodes are offset from the associated node contact holes so as not to have the minimum dimension in the planar configuration thereof, and cylinders are multiplied on a base portion of the storage electrode.

Semiconductor memory device having capacitor-over-bitline cell with

There is provided a semiconductor device, including: a semiconductor substrate having a major surface; a first insulating film formed on the major surface of the semiconductor substrate; a plurality of first conductive members spaced apart from each other on the first insulating film and formed to be connected to the semiconductor substrate; a plurality of storage electrodes formed on the first insulating film at positions respectively corresponding to the first conductive members; a plurality of high-permittivity films respectively stacked on the plurality of storage electrodes; a plurality of first counter electrodes respectively stacked on the plurality of high-permittivity films; a second insulating film, having a permittivity much lower than a permittivity of each of the high-permittivity films, for insulating the first conductive members, the high-permittivity films, and the first counter electrodes, respectively; and a second counter electrode, formed on the second insulating film, for connecting adjacent first counter electrodes on an upper surface of the second counter electrode, and a method of manufacturing the semiconductor device.

Method of making a semiconductor device

In a method for forming a capacitor in a semiconductor device, an insulating film is formed on a semiconductor substrate, and an opening is formed through the insulating film. Then, a conductive film is formed to cover a side wall surface of the opening and an upper surface of the insulating film, and a whole surface is mechanically ground so as to selectively remove the conductive film on the upper surface of the insulating film so that the conductive film remains only in an inside of the opening. The remaining insulating film is removed so that a cylindrical electrode is formed of an upstanding remaining conductive film having the same height as the thickness of the removed insulating film.

Method for forming a cylindrical stacked capacitor in a semiconductor

Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capacitor having a capacitor electrode connected to the source region through a contact hole provided in the first and second insulating film.

Semiconductor memory device having trench isolation regions and bit

In a method for manufacturing a semiconductor device incorporating a DRAM section and a logic circuit section, a refractory metal layer is formed to cover a bit line of the DRAM section, and a gate electrode and impurity diffusion regions of the logic circuit section. Then, a heating operation is performed upon sadi refractory metal layer, so that metal silicide layers are formed in the bit line of the DRAM section, and the gate electrode and the impurity diffusion regions of the logic circuit section.

Method for manufacturing semiconductor device incorporating DRAM section

Method of making a semiconductor memory device with improved capacitor

In a method of manufacturing an insulation layer on a semiconductor substrate, a first insulation film is deposited on the semiconductor substrate more thicker than a wiring layer formed on the semiconductor substrate. The first insulation film is mechano-chemically polished to expose a void formed in the first insulation film. The first insulation film is etched to widen an entrance portion of the void. A second insulation film is formed on the first insulation film to be embedded into the void. The second insulation film is etched at least to the first insulation film, with a part of the second insulation film left within the void. The exposed first insulation film and the left second insulation film has a flat surface.

Growing community of inventors

Tokyo, Japan

Masato Sakao