Kabushiki Kaisha Toshiba

Fujitsu General Limited

Masato Oda

Shinichi Yasuda

Kosuke Tatsumura

Koichiro Zaitsu

Mari Matsumoto

Shinobu Fujita

Keiko Abe

Kiwamu Sakuma

Tetsufumi Tanamoto

Kumiko Nomura

Haruka Kusai

Yinghao Ho

Yoshihisa Iwata

Yoshiaki Saito

Hideyuki Sugiyama

Tomoaki Inokuchi

Atsuhiro Kinoshita

Atsushi Kawasumi

Reika Ichihara

Takao Marukame

Hiroyuki Hamano

Kazutaka Ikegami

Mizue Ishikawa

Nobuyuki Ashikaga

Shuou Nomura

Makoto Shibuya

Shinobu Moniwa

Satomi Ebihara

Tomomi Takahashi

Yasuhiko Nagamori

Hideyuki Umenaka

Hiroyuki Tokimoto

Ryouhei Kondo

Jun Kakudate

Tsutomu Nagashima

Shinnji Sugiyama

An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.

Integrated circuit, test method for testing integrated circuit, and electronic device

A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.

Semiconductor integrated circuit

A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.

Memory circuit and electronic device

A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

Reconfigurable semiconductor integrated circuit

A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresponding one of the fifth wirings.

Semiconductor integrated circuit having programmable logic device and resistive change elements

A configuration memory circuit according to an embodiment includes: a first and second wirings; and a first to eighth transistors, the first and fourth transistors having a first-conductive-type, the second, third, fifth, and sixth transistors having a second-conductive-type, the first to third transistors being connected in series, the fourth to sixth transistors being connected in series, gates of the first and third transistors being connected to the first wiring, one of a source and a drain of the seventh transistor, and the first wiring, a gate of the second transistor being connected to a third wiring, gates of the fourth and sixth transistors being connected to the second wiring, one of a source and a drain of the eighth transistor, and the second wiring, a gate of the fifth transistor being connected to the third wiring, gates of the seventh and eighth transistors being connected to a fifth wiring.

Configuration memory circuit

An integrated circuit according to an embodiment includes: a first block including a first logic block configured to perform a logical operation, a first switch block circuit configured to control connection and non-connection with the first logic block, and a second switch block circuit configured to control connection and non-connection with the first logic block; and a second block including a second logic block configured to perform a logical operation, a third switch block circuit configured to control connection and non-connection with the second logic block, and a fourth switch block circuit configured to control connection and non-connection with the second logic block, wherein the first switch block circuit is mutually connected with the third and fourth switch block circuits, and the second switch block circuit is mutually connected with the third and fourth switch block circuits.

Integrated circuit and electronic device

An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.

Integrated circuit and electronic apparatus

An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a third terminal connected to the second terminal, and a fourth terminal; a first wiring line connected to the first terminal of the anti-fuse element; and a drive circuit configured to supply a plurality of potentials to the first terminal of the anti-fuse element, the drive circuit being connected to the first wiring line, the potentials being different from each other.

Integrated circuit

According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements.

Multi-context configuration memory

According to an embodiment, a reconfigurable semiconductor integrated circuit includes first and second blocks. The first block includes first memories; and second memories; a selector selecting one first memory and one second memory; a first logic circuit whose logic is determined according to data read from the selected first memory; and a first switch circuit that is connected to first wires and switches connection between the first wires according to data read from the selected second memory, a part of the first wires being connected to the first logic circuit. The second block includes third and fourth memories; a second logic circuit whose logic is determined according to data read from the third memory; and a second switch circuit that is connected to second wires and switches connection between the second wires according to data read from the fourth memory, a part of the second wires being connected to the second logic circuit.

Reconfigurable semiconductor integrated circuit and electronic device

A semiconductor integrated circuit according to an embodiment includes: N (&#x2267;1) input wiring lines; M (&#x2267;1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (&#x3e;M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines.

According to one embodiment, a reconfigurable logic circuit device includes a memory circuit including a cell group which includes unit cells connected in series, a control circuit connected to the unit cell at one end of the cell group, and an output terminal connected to the unit cell at the other end of the cell group; and a switch circuit connected to the output terminal and controlled by a signal from the memory circuit. Each of the unit cells includes a select element including first and second terminals and a control terminal to which a control signal is input, and a memory element including a third terminal connected to the first terminal and a fourth terminal connected to the second terminal.

Reconfigurable logic circuit device

According to an embodiment, a reconfigurable semiconductor integrated circuit includes memories connected in parallel, a logic circuit whose logic is defined according to data output of one of the memories, a signal output unit, and a switching unit. The signal output unit includes output terminals corresponding to the respective memories. Each terminal outputs a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit. The signal output unit is configured to output the selection signal in a cyclic manner over the terminals so that one terminal outputs the selection signal and the others output the non-selection signal. The switching unit is configured to set a route between a first output terminal and a second output terminal of the terminals to an open state or a closed state. The route bypasses at least a single output terminal.

A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

Growing community of inventors

Yokohama, Japan

Masato Oda