Hitachi, Ltd.

Masato Mogaki

Katsuaki Hongyo

Katsuyoshi Suzuki

Keiji Kojima

Yoshiki Matsuda

Yoshinori Kitahara

Seiji Futatsugi

Naoki Katoh

Hiromitsu Yamada

Tomonari Sakagami

Ikutane Miyamaru

A computer program stored on a storage medium for performing wiring condition processing for a semiconductor integrated circuit. The computer program when executed causes a computer to perform the steps of creating layout information to determine a layout of devices on the semiconductor integrated circuit based on logic information describing connections of the devices on the semiconductor integrated circuit, determining a virtual wiring path from the layout information and calculating a wiring delay value based on the virtual wiring path. Other steps performed upon execution of the computer program include upon the calculated wiring delay value of the virtual wiring path exceeding a predetermined reference value, calculating a wiring delay value of the virtual wiring path when a wide wiring line is used at a predetermined usage ratio.

Semiconductor integrated circuit wiring condition processing program

When gates are placed on a chip, an average delay budget per stage of the gate is calculated from a target machine cycle time and the number of logic gate stages between an initial point flip-flop and a terminal point flip-flop, a wire length limitation of a net of each stage is calculated from the average delay budget and delay characteristics of the gate of each stage, and the gates are placed by using the wire length limitation as a target function.

Electronic parts placement method and a computer readable medium having an electronic parts placement program

In a computer-aided design (CAD) method for the intra-chip wiring in a hierarchical implementation design of a semiconductor integrated circuit, wiring pattern spaces from block edge terminals are guaranteed while preventing any wiring detour in inter-block nets. Logical line connecting information and implementation information such as contours of parts and terminal positions are inputted from a logical file and a library to extract block edge terminals so as to define a block boundary in accordance with layout positions of parts to be allocated. On the block boundary defined, one virtual terminal is generated for each block edge terminal to dispose wirings between the block edge terminals and the associated virtual terminals. An intra-block net wiring is then achieved without a short circuit to the wirings between the block edge terminals and the associated virtual terminals. Finally, the virtual terminals and the wiring pattern between the block edge terminals and the associated virtual terminals are deleted.

Hierarchical wiring method for a semiconductor integrated circuit

In a wiring condition processing method for a semiconductor integrated circuit layout information, which determines the layout of devices on the semiconductor circuit, is created based on logic information describing a connection relationship among the devices on the semiconductor. Next, a virtual wiring path is determined from the layout information. Based on the virtual wiring path, a wiring delay value is calculated. If the wiring delay value exceeds a predetermined reference value, one or more of information on the usage ratio of a wide wiring line, information on the usage ratio of a wiring layer with a small wiring load capacity, information on the usage ratio of a parallel wiring line, and information on the usage ratio of a wiring material are added to the information on the virtual wiring path to create wiring condition information.

Semiconductor integrated circuit wiring condition processing method

A portable pen pointing device and a processing system with pen pointing device which can be easily used. The portable pen pointing device includes a memory for storing user's specific penmanship/handwriting information and a pen interface unit for supplying the user's specific penmanship/handwriting information to a processor body of the processing system. The processor body interprets a writing sample on the basis of the user's specific penmanship/handwriting information supplied from the portable pen pointing device through the pen interface unit thereof. With this construction, there is no need to read information from a storage medium such as a flexible disk in which a user's specific dictionary for penmanship/handwriting interpretation is written. Also, an operation of establishing a certain writing environment becomes unnecessary or easy.

Portable pen pointing device and a processing system with pen pointing

According to the present invention, in a knowledge based system having rules each constructed of 'IF condition clause, THEN action clause', a working memory for storing a data group describing an inference object to which a rule is applied, and an inference engine, in selecting one instantiation from a conflict set, a rule for each instantiation is executed in accordance with the action clause of the rule, the execution results are evaluated by using an evaluation knowledge, and the evaluation results are compared to select the instantiation having a higher evaluation value. The data changed by the rule execution process for an instantiation aborted after the evaluation is recovered to the original state. The invention is applicable to the placement method of elements and interconnections within a semiconductor integrated circuit.

Growing community of inventors

Hadano, Japan

Masato Mogaki