Fujitsu Corporation

Masato Mitsuhashi

Takeshi Kitahara

Atsushi Fujihira

Yoshiyuki Shirai

One aspect of the present invention is a clock switching circuit for switching between asynchronous first clock and second clock when connecting or disconnecting an interface cable having a hot-plug function. The clock switching circuit includes a first group of flip-flops for receiving an interface disconnection signal that corresponds to disconnection and connection of the interface cable in response to the first clock, and a second group of flip-flops for receiving the interface disconnection signal in response to the second clock.

Clock switching circuit for a hot plug

A microcontroller capable of operating in any one of several operation modes and includes first latch circuits which latch first mode signals from first external nodes at a first timing and second latch circuits latching second mode signals from the same external nodes at a second timing. Operation modes are switched by using the mode signals stored in the first and second latch circuits, so that a single external node can provide two bits for expressing the operation modes. Thus, the number of bits used to represent the mode signal can be increased without increasing the number of external nodes. Also provided is a microcontroller in which the time required for a test can be reduced by eliminating the waiting period for clock generation to be stabilized.

Multiple operation mode microcontroller

A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory coincides with the fetching of one block data. Further, a notification means notifies the state of the fetching operation to an external cache memory. Therefore, the external cache memory can confirm whether a block-in operation of the microprocessor is broken or not, and the contents of the external cache can correctly coincide with the contents of the internal cache and the main memory by carrying out a steal operation, so that the operational reliability of a computer system can be increased.

Data processing device for maintaining coherency of data stored in main

A block access system using a cache memory comprises a first control circuit for producing a block access request for requesting read-out of all data included in a block of a predetermined size in response to an access request from an operation unit and inputting the data read out from a main memory unit into a cache memory, and a second control circuit for reading out data from the main memory unit and sending back to the first control circuit a response signal which indicates any one of execution and cancellation of the requested block access in response to the block access request from the first control means. Memory addresses necessary for reading out all the data in one block are produced by the first control circuit when the block access request is cancelled. Alternatively, memory addresses are supplied by the second control circuit when the block access request is executed.

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Kawasaki, Japan

Masato Mitsuhashi