Shindengen Electric Manufacturing Company Limited

Masato Mikawa

Toshiki Matsubara

Nobutaka Ishizuka

Ryohei Kotani

Hiroshi Oshino

Mizue Kitada

Shinji Kunori

Hiroaki Shishido

Kosuke Ohshima

Masahiro Kuriyama

Toru Kurosaki

A semiconductor device of an embodiment includes an overvoltage protection diode in which an N-type semiconductor layer and a P-type semiconductor layer, formed on an insulating film in a voltage supporting region, are alternately disposed adjacently to each other. The overvoltage protection diode is disposed at a corner portion on the upper face of the insulating film, and extends from the corner portion to the center portion of the semiconductor substrate.

Semiconductor device

A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer. The concentration peak of the p-type impurities is disposed in a non-boundary region between a boundary region and a boundary region.

Semiconductor device and method of manufacturing the same

A semiconductor switch SW that includes a collector electrode C, an emitter electrode E and a gate electrode G, a Zener diodeA configured to include one end electrically connected to the collector electrode C, the other end electrically connected to the gate electrode G, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, a Zener diodeB configured to include one end electrically connected to the gate electrode G, the other end electrically connected to the emitter electrode E, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, are provided. The Zener diodeA and the Zener diodeB are configured so as not to allow the voltage of the gate electrode G to be increased to an on-threshold voltage of the semiconductor switch SW in the reverse bias application state.

A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.

In a semiconductor device according to an embodiment, ends of conductor portions are electrically connected to an overvoltage protection diode so that depletion occurs in a diffusion layer in a portion near an insulating film in a reverse bias application state, and/or ends of conductor portions are electrically connected to the overvoltage protection diode so that depletion occurs in a peripheral semiconductor region in a portion near the insulating film in the reverse bias application state.

A semiconductor device having high withstand strength against destruction. The semiconductor deviceincludes guard buried regionsof second conductivity type concentrically provided on a resistance layerof first conductivity type and base diffusion regionsare provided inside of the guard buried regionand base buried regionsof the second conductivity type are provided on the bottom surface of the base diffusion regions. A distance between adjacent base buried regionsat the bottom of the same base diffusion regionis Wm, a distance between adjacent base buried regionsat the bottom of the different base diffusion regionsis Wm, and a distance between the guard buried regionsis W. A ratio of an impurity quantity Qof the first conductivity type and an impurity quantity Qof the second conductivity type included inside the widthwise center of the innermost guard buried regionis 0.90&#x3c;Q/Qwhen Wm&#x3c;W&#x3c;Wm. When W&#x3c;Wm&#x3c;Wm, the ratio is Q/Q&#x3c;0.92 and when Wm&#x3c;Wm&#x3c;W, the ratio is 1.10&#x3c;Q/Q.

A semiconductor device having high withstand voltage is provided. An active grooveincludes a long and narrow main groove partand a sub groove partconnected to a longitudinal side surface of the main groove part, and a buried regionof a second conductivity type whose height is lower than the bottom surface of the base diffusion regionof the second conductivity type is provided on the bottom surface of the main groove part. An active groove filling regionof the second conductivity type in contact with the base diffusion regionis provided in the sub groove part. The buried regionis contacted to the base diffusion regionthrough the active groove filling region. Since one gate grooveis formed by the part above the buried regionin one active groove, the gate electrode plugsare not separated, which allows the electrode pattern to be simplified.

Semiconductor device and method for manufacturing thereof

A semiconductor device having high ruggedness is provided. The distance Wmbetween buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wmbetween buried regions positioned at the bottom of the same base diffusion region (Wm&#x3e;Wm). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.

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Hanno, Japan

Masato Mikawa