Panasonic Corporation

Socionext Inc.

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Masato Maede

Koichi Taniguchi

Toshiyuki Kojima

Masahiro Gion

Mitsuo Saitoh

Shiro Usami

Shozo Ochi

Naoki Nojiri

Ryo Ishikawa

Kazuto Fukuda

Masaya Hirose

Daisuke Matsuoka

Kinya Daio

Tomonari Nebashi

Hisaki Watanabe

Taishi Fujimoto

Shinji Kinuyama

A cooling unit includes a unit main body including a bottom portion, a peripheral wall portion rising from the peripheral edge of the bottom portion, and a seal for sealing an opening of the unit main body. The unit main body is joined to the seal through a plasticized region, and a void is defined in the peripheral wall portion of the unit main body.

Cooling unit and method for manufacturing cooling unit

A soft magnetic powder that can exhibit desirable soft magnetic characteristics. A dust core using the soft magnetic powder is also provided. The soft magnetic powder includes: a soft magnetic powder layer of an unoxidized soft magnetic material; a second oxide layer as an oxide with iron or boron residing around the soft magnetic powder layer; and a first oxide layer of an iron oxide residing around the second oxide layer. The first oxide layer and the second oxide layer reside in a region of 20 nm or more and 500 nm or less from a surface of the soft magnetic powder, and are absent in a region of more than 500 nm and 1,600 nm or less from the surface.

Soft magnetic powder, method for producing same, and dust core using soft magnetic powder

Provided herein is a soft magnetic alloy powder that can exhibit a high saturation flux density and desirable soft magnetic characteristics. A dust core using the soft magnetic alloy powder is also provided. The soft magnetic alloy powder is an Fe-based nanocrystalline soft magnetic alloy powder of a crystallized Fe-based amorphous soft magnetic alloy powder, and has a DSC curve with a first peak that is 15% or less of a first peak of the Fe-based amorphous soft magnetic alloy in terms of a maximum value.

Soft magnetic alloy powder and dust core using same

A soft magnetic alloy powder includes a first pulverized powder which has a particle diameter of 20 &#x3bc;m or more, a value of major diameter/minor diameter of 1.2 or more and 1.8 or less, and a flat plate shape, and a second pulverized powder which has a particle diameter of less than 3 &#x3bc;m, a value of major diameter/minor diameter of 1.1 or more and 1.6 or less, and a flat plate shape. A production method of a soft magnetic alloy powder, includes first processing of processing a soft magnetic alloy ribbon into a coarse powder, and second processing of pulverizing the coarse powder with a pulverizer.

Soft magnetic alloy powder, production method thereof, and dust core using same

Provided herein is a soft magnetic alloy powder that can exhibit a high saturation flux density and desirable soft magnetic characteristics. A dust core using such a soft magnetic alloy powder is also provided. A soft magnetic alloy powder is used that includes an amorphous phase, and an &#x3b1;Fe crystalline phase residing in the amorphous phase. The &#x3b1;Fe crystalline phase has a crystallite volume distribution with a mode of 1 nm or more and 15 nm or less, and with a half width of 3 nm or more and 50 nm or less.

Soft magnetic alloy powder, method for producing same, and dust core using soft magnetic alloy powder

A semiconductor chip including an internal circuit, a plurality of electrode pads and a plurality of I/O cells. The plurality of electrode pads are arranged on a first line, a second line and a third line. Each of the plurality of electrode pads arranged at least on the first and second lines overlaps corresponding one of the plurality of I/O cells in a plan view. The plurality of I/O cells are provided on a peripheral region of the semiconductor chip. Each of the plurality of I/O cells includes a protective circuit, and is connected to corresponding one of the plurality of electrode pads. The protective circuit includes a power source-side protective circuit provided between the corresponding one of the plurality of electrode pads and a power source wiring; and a ground-side protective circuit provided between the corresponding one of the plurality of electrode pads and a ground wiring.

Semiconductor integrated circuit device

In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

Semiconductor integrated circuit

An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.

Input/output circuit

In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.

Semiconductor chip

An oscillation circuit according to the present invention comprises a solid-state oscillator, an amplifier for feedback-controlling the solid-state oscillator, and ESD protecting circuits respectively connected to the input and output sides of the amplifier, wherein the ESD protecting circuit on the input side of the amplifier comprises an ESD protecting element whose constituent is a diode having a P-type diffusion layer and an N-type diffusion layer, and the ESD protecting circuit on the output side of the amplifier comprises an ESD protecting element whose constituent is an MOS transistor.

Growing community of inventors

Kyoto, Japan

Masato Maede