Hitachi, Ltd.

Renesas Technology Corp.

Masato Kunitomo

Shinpei Iijima

Hiroyuki Ohta

Masahiko Hiratani

Yuichi Matsui

Yuzuru Ohji

Yukihiro Kumagai

Tsuyoshi Fujiwara

Kazuaki Tokunaga

Takeshi Saikawa

Ryouichi Furukawa

Soichiro Tanaka

A highly accurate feature extraction is performed on a signal with temporal variation in amplitude, and this signal is restored to detect a state of a transmission source (output source) of this signal to be normal or abnormal. A signal processing method includes: separating a signal X into an oscillation signal with a constant amplitude Xand a signal with temporal variation in amplitude X, the separating performed by a signal separator; performing processing of dimensionality reduction, compression, or the like, on the oscillation signal Xso as to extract a feature value (information) included in the oscillation signal X; and outputting a restored signal X' that is restored from the oscillation signal Xby performing processing inverse to the processing of dimensionality reduction, compression, or the like, based on the extracted feature value, performing the processing, the inverse processing, and the outputting performed by a signal Xrestorer.

Signal processing system and signal processing method

A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450&deg; C. to 700&deg; C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.

Method of manufacturing semiconductor integrated circuit device comprising a memory cell and a capacitor

A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE LAYER FORMED OVER THE FIRST METAL LAYER AND A SECOND METAL LAYER FORMED OVER THE SECOND METAL SILICIDE LAYER

METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS

A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode,made of a ruthenium film and an upper electrode,made of a capacity insulating film,and a titanium nitride film and which is connected in series with a memory cell selection MISFET Qs formed on the main surface of a semiconductor substrate,. The capacity insulating film,is made of a multi layered film comprising two layered crystallized tantalum oxide films,and,each having a film thickness of 10 nm or less. The film thickness of the capacity insulating film,is set to 10 to 40 nm.

Method of making a memory cell having two layered tantalum oxide films

Growing community of inventors

Ome, Japan

Masato Kunitomo