Matsushita Electronics Corporation

Matsushita Electric Industrial Co., Ltd.

Masato Kanazawa

Takashi Uehara

Michikazu Matsumoto

Masahiro Yasumi

Shinichi Ogawa

Tatsuo Sugiyama

Kouji Tamura

A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

Method for fabricating a semiconductor device having contacts self-aligned with a gate electrode thereof

After forming a polysilicon film to be used as a gate electrode on a semiconductor substrate of silicon, an insulating thin film is deposited on the polysilicon film. Impurity ions are implanted into the polysilicon film through the insulating thin film, so as to form an amorphous layer on the surface of the polysilicon film. After removing the insulating thin film existing on the polysilicon film, a metal film is deposited on the amorphous layer. A reaction is caused between the amorphous layer and the metal film through annealing, so as to form a metal silicide layer on the surface of the polysilicon film.

Method of manufacturing semiconductor device

A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. First connection holes are formed at specified positions of the first interlayer dielectric film layer. A first conductive film layer is formed in a region including at least the first connection holes and is composed of three layers by sequentially laminating a barrier metal film, an aluminum alloy film, and an anti-reflection film. A second interlayer dielectric film layer is formed on the first conductive film layer and is composed of a lower layer of silicon oxide film, an intermediate layer of silicon oxide film made of inorganic silica or organic silica, and a upper layer of silicon oxide film. Specified positions of the second interlayer dielectric film layer are selectively removed to form second connection holes. A second conductive film layer is formed thereon and is composed of two layers of refractory metal film in the bottom layer and aluminum alloy film in the top layer.

Semiconductor device including interlayer dielectric film layers and

A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. The first interlayer dielectric film is made of a BPSG film formed by the method of atmospheric pressure chemical vapor deposition. First connection holes are formed at specified positions of the first interlayer dielectric film layer. A first conductive film layer is formed in a region including at least the first connection holes. The first conductive film layer is composed of three layers by sequentially laminating a barrier metal film, an aluminum alloy film, and an anti-reflection film. On the first conductive film layer formed in a specified pattern, a second interlayer dielectric film layer is formed. The second interlayer dielectric film layer is composed of a lower layer of silicon oxide film, an intermediate layer of silicon oxide film made of inorganic silica or organic silica, and an upper layer of silicon oxide film. Specified positions of the second interlayer dielectric film layer are selectively removed. The removed regions become second connection holes. A second conductive film layer is formed thereon. The second conductive film layer is composed of two layers of refractory metal film in the bottom layer and aluminum alloy film in the top layer.

Growing community of inventors

Kyoto, Japan

Masato Kanazawa