Hitachi, Ltd.

Masato Iwabuchi

Katsumi Ogiue

Satoru Isomura

Masami Usami

Masanori Odaka

Akihisa Uchida

Osamu Yamashiro

Kazumichi Mitsusada

Kazuhiro Akimoto

Takahisa Nitta

Goichi Yokomizo

Takeo Uchiyama

Mikako Miyama

Masami Kinoshita

Saburo Hojo

Takasi Oomori

Shigeharu Murata

Yoshino Sakai

Munehiro Ogawa, Deceased

Hitoshi Sugihara

A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.

Mixed mode simulation method and simulator

In a gate array with a RAM which is disposed between first and second logic circuit blocks each of which having plural logic gates, by-pass signal lines which interconnect the logic circuit blocks are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines, such as word lines of the RAM, formed from a layer which is adjacent to the by-pass signal lines are disposed, with respect to a plan view layout arrangement of the main surface of a chip, so as to intersect the latter at right angles. In addition, interconnection pitches of signal lines in different wiring layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

Semiconductor IC device having a RAM interposed between different logic

A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.

Hold-type latch circuit with increased margin in the feedback timing and

A semiconductor memory device for use in a digital data processor together with a central processing unit (CPU) receives address signals which are validated for a time period n times as long as the machine cycle of the CPU, and it stores therein input data items which are validated for a cycle equal to the machine cycle of the CPU or delivers therefrom output data items which are validated for a cycle equal to the machine cycle of the CPU.

Semiconductor integrated circuit device and digital processor employing

In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layer which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Semiconductor integrated circuit device having a gate array with a ram

In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

Semiconductor integrated circuit device having a gate array with a RAM

A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.

Semiconductor memory device having a timing generator circuit which

In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Semiconductor integrated circuit device

The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.

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Hachioji, Japan

Masato Iwabuchi