Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Masato Ishii

Jun Kitahara

Kenichi Saitou

Masaya Umemura

Patrick Hamilton

Nobuhiko Hara

Tadaaki Isobe

Shigeo Takeuchi

Toshimitsu Ando

Sawamura Shinichi

Hitoshi Takeoka

Junichi Miyata

Sawamura Shin'ichi

Takahiro Ogimoto

Osamu Arakawa

An information processing apparatus includes a volatile storage unit and a nonvolatile storage device for storing at least algorithm information for processings executed by the processing unit, processed data inclusive of display-destined data generated in the storage unit and circuit state information concerning individual circuits incorporated in the information processing apparatus during operation of the information processing apparatus, and a control unit for setting a predetermined operation-mode state in accordance with predetermined rules of state transition so as to store selectively the algorithm information, the processed data and the circuit state information in the volatile storage unit and nonvolatile storage device in dependence on the conditions imposed externally through manipulation of the apparatus, whereby the time required for activating or resuming the information processing apparatus is reduced.

Information processing apparatus that can hold internal information

A battery assembly unit and a method of charging the same for applying constant current/constant voltage charging to a battery assembly in which a plurality of battery cell groups each having battery cells each being rechargeable and increasable in electromotive force as charging proceeds are connected in series. There are provided a reference charging voltage circuit for generating charging reference voltages serving as voltages referenced to electromotive force levels of the individual battery cell groups on the basis of charging voltage applied across the battery assembly and changeable with time, and comparison circuits each adapted to compare an electromotive force level across each of the plurality of battery cell groups connected in series with the charging reference voltage. Further, bypass circuits are provided each of which connected in parallel across each of the plurality of battery cell groups connected in series and when an electromotive force of a battery cell group exceeds the charging reference voltage, bypasses the charging current by an amount corresponding to a difference.

Battery unit having a plurality of rechargeable battery cells and method

A crossbar switch and a broadcast communication method for use in a parallel computer that avoids an occurrence of deadlock states caused by conflicts for use of a path by a plurality of broadcast messages. The parallel computer, in which a plurality of nodes are connected by a crossbar switch, is provided with output buffer monitoring circuits. A vacant capacity of each of the output buffers is monitored. The vacant capacity of each output buffer is monitored to ensure that it is sufficiently high to store the broadcast message. The parallel computer is also provided with a priority controller in which one of a plurality of broadcast messages is selected when they are input. The message transmission-permit signal is issued to the packet selector circuits only when the broadcast transmission-permit signals for all the output ports for transmitting the message are issued. The broadcast transmission-permit signals are issued only when the vacant capacity of each output buffer is sufficiently high to store a broadcast message.

Crossbar switch system for always transferring normal messages and

A multistage interconnection network capable of performing highly reliable communications with less hardware. In the multistage interconnection network for interconnecting a plurality of nodes, the first and final stages each have switches two times as large as the number of switches at an intermediate stage. Two output ports of each node are connected to the input ports of different first stage switches, and two input ports are connected to the output ports of final stage different switches. The input ports of switches of the intermediate stage are connected to the output ports of first stage different switches, and the output ports are connected to the input ports of final stage different switches. At least one output port of each switch at the first stage is directly connected to at least one input port of an optional switch at the final stage.

Multistage interconnection network and parallel computer using the same

A parallel computer system includes a plurality of processor units, a data transfer network for interconnecting the processor units, a synchronizing network for allowing program execution to be performed synchronously by the individual processor units, a connecting unit for connecting the individual processor units and the synchronizing network, and an input unit connected to the synchronizing network. The connecting unit connects selectively the individual processor units to the synchronizing network in accordance with information inputted via the input unit. With the parallel computer system, a program can be executed synchronously in parallel by using a desired number of processor units of those incorporated in the system, whereby availability of processor resources of the system can be enhanced.

Parallel computer system

Growing community of inventors

Sagamihara, Japan

Masato Ishii