Fujitsu Corporation

Masato Ishiguro

Hideo Monma

Tetsuo Kawano

Hajime Kubosawa

Masayuki Takahashi

A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprises a plurality of input/output cells being arranged in a peripheral region on a semiconductor chip; a plurality of basic cell columns each comprising a plurality of basic cells arranged in a predetermined direction, each basic cell constituting transistors; an interconnection region formed on the chip, for accommodating a data bus; and a plurality of latch cells being arranged in the basic cell columns, for keeping a potential of a data bus laid on the interconnection region to prevent the data bus from being changed into a floating state, each latch cell comprising transistors, each of which has a driving capability smaller than that of each transistor of the basic cell.

Master slice type integrated circuit

A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.

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Machida, Japan

Masato Ishiguro