Fujitsu Corporation

Masato Hashizume

Tatsuya Oku

Yasuo Takami

Hiroshi Nishida

Hiroyuki Iwaki

Masaki Hiromori

Yuji Kamura

Yoshihisa Ikeda

Megumi Shibata

Takanori Yasui

Toshiaki Asai

Chikashi Hashimoto

Yoshinari Oshio

Hisanori Okano

Seiji Matsuzaki

A communication device includes a reception buffer configured to receive a pulse signal cyclically transmitted from a transmission source device via a transmission line; a branch circuit configured to generate a branch pulse signal by branching the pulse signal; a delay circuit configured to add a predetermined delay time to the generated branch pulse signal; and a transmission buffer configured to transmit the branch pulse signal to which the predetermined delay time was added to the transmission source device via the transmission line.

Communication device, pulse signal delay adjustment method and communication system

A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.

Communication apparatus having clock interface

A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.

Network device

An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each state number. A monitoring circuit, using the upper and lower limit values for the present state number, judges the value of current consumption detected by a current detection circuit and detects whether there is abnormality in operation.

Abnormal circuit operation detection system

A transmission device and an integrated circuit improved in quality and reliability of digital transmission control. A memory stores an input signal, write address generating means generates a write address for writing in the memory, and read address generating means generates a read address for reading from the memory. Phase state monitoring means monitors a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided. When the coincident phase state or the unstable phase state is detected, reset signal output means outputs a reset signal to the write and read address generating means such that the phase relation between the write and read addresses is brought to an optimum phase relation.

Transmission device and integrated circuit

Growing community of inventors

Kawasaki, Japan

Masato Hashizume