Fujitsu Corporation

Masato Abe

Fumitaka Asami

Fusao Seki

A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal.

Odd-number frequency divider and method of constituting the same

In a matrix operation apparatus for calculating output signals by multiplying input signals with coefficients, a plurality of matrix element calculating circuits multiply the input signals with corresponding coefficients to obtain matrix elements. An output calculating circuit adds and subtracts the obtained matrix elements to obtain one of the output signals. In this case, the coefficients are changed by a coefficient changing circuit which also controls the output calculating circuit, and thus the output calculating circuit generates the plurality of output signals in a time-divisional manner.

Color signal matrix circuit

A code converter includes an extraction device for extracting a reference level from a binary-coded input signal, which is offset at a predetermined voltage level and which varies arbitrarily with the same polarity as the voltage level. A twos-complement conversion device, connected to the extraction device, converts the reference level into a twos-complement value. A creation device, connected to the extraction device and the twos-complement conversion device adds an output signal of the twos-complement conversion device and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.

Code converter and encoder for converting a unipolar binary coded signal

A signal processing circuit comprises a constant value generating circuit for generating a constant value (.alpha..sub.i) corresponding to a delay time (d.sub.i) for an input signal (V.sub.i (t)); an adding/subtracting circuit for alternately adding the constant value to the input signal and subtracting the constant value from the input signal for every half period of the input signal; and an amplitude correcting circuit for correcting an amplitude of an output signal of the adding/subtracting circuit for every half period of the input signal so that a delayed output signal (V.sub.o (t)) having a waveform corresponding to a waveform of the input signal is produced.

Signal processing circuit

Noise pulses having both polarities which are superposed on an input signal having a binary state of H/L levels forming a rectangular waveform, are suppressed or eliminated before transferring the input signal to an output stage. A noise pulse suppressing circuit is provided which comprises a latch circuit, a counter circuit, and a logic circuit including NAND gates and INVERTERs. For the latch circuit and the counter circuit, D-type flip-flops are also utilized. The input signal is inputted to a data input terminal of a flip-flop of the latch circuit and outputted from the data output terminal thereof. The latch circuits are triggered by a pulse signal applied to a clock terminal thereof. The above triggering pulse signal is generated by the counter circuit and the logic circuit, and it has a short pulse waveform responding to the input signal but delayed. No pulse in the output is produced which corresponds to the noise pulses in the input signal.

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Kawasaki, Japan

Masato Abe