Kabushiki Kaisha Toshiba

Masataka Takebuchi

Fumitaka Arai

Seiichi Mori

Toshiharu Watanabe

Kazuaki Isobe

Daisuke Tohyama

Hidemitsu Ogura

Yoshiharu Hirata

Hirohito Taneda

Kazuhiro Utsunomiya

Yoshito Suwa

Noriyasu Ikeda

In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Field effect type semiconductor device and method for manufacturing the same

A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film.

Semiconductor device and method of manufacturing the same

A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Semiconductor device including nonvolatile memory and method for fabricating the same

A semiconductor device including a nonvolatile memory formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

Semiconductor device including nonvolatile memory

A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.

Semiconductor device having MISFETs

In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density of a gate insulating film of the p-channel IGFET. With respect to a manufacturing method, a region where the gate insulating film of the p-channel IGFET is covered by a thick buffer silicon oxide film when nitrifying the tunnel insulating film of the non-volatile memory element. The buffer silicon oxide film can be reliably removed when the gate insulating film is formed, because no nitride film is made between the substrate and the buffer silicon oxide film.

Semiconductor device including insulated gate field effect transistors

Method of manufacturing memory device including insulated gate field effect transistors

An n-type diffused layer is formed in a p-type semiconductor substrate. A control gate electrode of a memory cell MC is connected with a metal interconnect of a first layer and the metal interconnect is connected with the diffused layer. Moreover, a metal interconnect of the first layer is connected with a metal interconnect of a second layer. An interconnect of the second layer is connected with the output node of a row decoder.

Semiconductor device having multilayer metal interconnection

A high-speed and highly-integrated semiconductor device and a producing method thereof, which can reduce resistance between a gate electrode and a wiring layer on the gate electrode and can make an element minute, are provided. The gate electrodes on a semiconductor substrate, diffusion layers formed in a surface region of the semiconductor substrate, buried electrodes formed on the semiconductor substrate so as to be connected to the diffusion layers respectively, an interlayer insulating film buried in spaces between the gate electrodes and in spaces between the gate electrodes and the buried electrodes, and wiring layers formed so as to be connected to the gate electrodes or to the buried electrodes are provided. A height of surfaces of the gate electrodes, a height of surfaces of the buried electrodes and a height of a surface of the interlayer insulating film are equal, and the surfaces of the gate electrodes, the buried electrodes and the interlayer insulating film form a plane. The wiring layers formed on the plane so as to be directly connected to the surfaces of the gate electrodes and the buried electrodes.

MOS gate structure semiconductor device

A semiconductor memory device includes different types of memory matrices adjacently arranged such that bit lines are aligned in the same cell matrix region, a column decoder for selecting the bit lines of the memory matrix, and a row decoder for selecting the row lines of the memory matrix. Therefore, a semiconductor memory device having many types of memory matrices can be highly integrated in the same cell matrix region in the same layout.

Semiconductor memory device

According to this invention, a semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of gate insulating films having different thicknesses and a first conductive film formed on the insulating films and electrically floating from the semiconductor substrate through the insulating films. These at least two types of gate insulating films include a first insulating film formed on said semiconductor substrate and a first diffusion layer of a conductivity type and a second insulating film formed on said semiconductor substrate and a second diffusion layer, of the opposite conductivity type, which is isolated from the first diffusion layer. The first conductive film is formed on the first and second insulating films. A part of the first insulating film between the first conductive film and the first diffusion layer is constituted by a third insulating film having a thickness smaller than that of the first insulating film.

Method of manufacturing semiconductor non-volatile memory device having

A non-volatile semiconductor memory device includes a voltage supply circuit for supplying a positive voltage to the source line or bit line (to which a low biasing voltage is conventionally applied) with respect to each of non-volatile memory cells in a memory cell array in a data read mode. Since this voltage supply circuit applies the positive voltage to the memory cells in the data read mode, an effect equivalent to back gate biasing of the memory cells can be achieved. Accordingly, a memory cell in an overerase state has, a positive threshold voltage in the data read mode.

Growing community of inventors

Kanagawa-ken, Japan

Masataka Takebuchi