Matsushita Electric Industrial Co., Ltd.

Masataka Osaka

Tsutomu Sekibe

Tomohiko Kitamura

Hideyuki Kanzaki

A memory control unit and a memory unit is connected to each other by a bus used for transfer of address, data and control signals. The memory control unit outputs a first command including a first predetermined location in the memory unit, to the memory unit. The memory control unit outputs a second command including a second predetermined location in the memory unit, to the memory unit when a predetermined time period has elapsed since the output of the first command.

Information processing apparatus, memory, information processing method, and program

A cross-bus switch apparatus which establishes simultaneously two or more pairs of connections between (i) a source bus arbitrarily selected from a plurality of source buses connected to one or more source apparatuses and (ii) a destination bus arbitrarily selected from a plurality of destination buses connected to one or more destination apparatuses. The cross-bus switch apparatus includes: a plurality of cross-bus switch units. The plurality of source buses are grouped into a plurality of source bus groups which are each connected to one of the plurality of cross-bus switch units. The plurality of destination buses are grouped into a plurality of destination bus groups which are each connected to one of the plurality of cross-bus switch units. Each cross-bus switch unit is connected to either (i) a source bus group or a destination bus group, or (ii) a source bus group and a destination bus group.

SYSTEM LSI AND A CROSS-BUS SWITCH APPARATUS ACHIEVED IN A PLURALITY OF CIRCUITS IN WHICH TWO OR MORE PAIRS OF A SOURCE APPARATUS AND A DESTINATION APPARATUS ARE CONNECTED SIMULTANEOUSLY AND BUSES ARE WIRED WITHOUT CONCENTRATION

A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI writes into the transfer rate information storage unit the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.

Memory control device and LSI

A system integrated circuit that identifies the cause of a malfunction even if the number of output terminals of a system LSI to be assigned to internal buses in the system LSI is strictly restricted. Comparators to are connected to any of a plurality of buses. Each comparator judges whether a certain expected value matches data transferred on a bus connected to the comparator. The selector unit selects one of the plurality of buses in accordance with the judgement result of the comparator, and outputs data transferred on the selected bus to outside the system integrated circuit so that an observer can observe internal state of the system integrated circuit from outside.

System integrated circuit

A digital broadcast receiving apparatus, for receiving a plurality of pieces of compressed still image data repeatedly transmitted from a digital broadcast transmitting apparatus and for outputting a still image selected by a user as a TV signal, fetches still image data into a main memory prior to a selecting operation made by the user, expands still image data of a still image selected by the user using an AV decoder of an MPEG decoder, and outputs an image signal of the selected still image according to the expanded still image data.

Digital broadcast receiving apparatus for displaying still images at high speed

In a system bus connected to at least one CPU having a cache memory used for increasing memory access speed in an engineering workstation or the like, a main memory controller including a status memory for storing owned and unowned statuses in a main memory and a cache memory of data associated with an access operation to a system bus connected to at least one CPU having a cache memory performed by an access means of a CPU or the like, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before the time for outputting a data invalidating signal from the cache memory elapses in the case of the owned status and for reading the data in the cache memory after the data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in the status memory according to the result of the monitoring.

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Osaka, Japan

Masataka Osaka