Matsushita Electric Industrial Co., Ltd.

Hitachi, Ltd.

Renesas Electronics Corporation

Panasonic Corporation

Renesas Technology Corp.

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Intellectual Property Corporation of America

Masataka Minami

Masayuki Kozuka

Koichiro Ishibashi

Motoji Ohmori

Kenji Tagawa

Toshihisa Nakano

Shuji Ikeda

Kenichi Osada

Makoto Tatebayashi

Masaya Yamamoto

Teruto Hirota

Takahiro Nagano

Taihei Yugawa

Takahiro Yamaguchi

Atsuo Watanabe

Hiroyuki Mizuno

Kaoru Murase

Yutaka Kobayashi

Shoji Shukuri

Yoji Nishio

Masayuki Miyazaki

Atsushi Hiraishi

Takeshi Matsuo

Yoshiaki Yazawa

Akihiro Tamba

Yasuo Kaminaga

Fumiaki Suzuki

Yuki Koide

Tsuyoshi Sakata

Makoto Morise

Takahiro Miki

Shunji Harada

Masao Nonaka

Toshiaki Yamanaka

Hiroki Shimano

Kenichi Shimada

Hiroji Ozaki

Takahide Ikeda

Masanori Ikeda

Kazushige Sato

Shigeki Obayashi

Naohiro Momma

Mitsuhiro Inoue

Tomoyuki Nonomura

Tadashi Kameyama

Yukitoshi Tsuboi

Mitsuru Hirao

Naoya Arisaka

Yoshihisa Fukushima

Yoshiho Gotoh

Wataru Ikeda

Kazuo Yano

Kenichi Kuroda

Mitsuru Hiraki

Hideyuki Matsuoka

Shinichiro Kimura

Akio Nishida

Eiichi Murakami

Yasuko Yoshida

Ryuichi Okamoto

Keiichi Yoshizumi

Yoshiyuki Miyabe

Shiro Kamohara

Atsushi Saso

Kazuo Kajimoto

Takashi Nishida

Masato Yamamichi

Kazuhisa Watanabe

Ryota Miyazaki

Tetsuo Maeda

Kazuoki Otani

Ryuichi Izawa

Kouichi Seki

Osamu Kawashima

Youkou Wakui

Joseph Mccrossan

Joseph Mc Crossan

The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.

Abnormal power supply voltage detection device and method for detecting abnormal power supply voltage

A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R-R), and drives the nMOS transistors MN-MNby the subdivided input voltages Vi-Vieach having different resistive subdivision ratios, respectively. The pMOS transistor MPis provided in common for the pMOS transistors MP-MP, and configures a current mirror circuit with each of the pMOS transistors MP-MP. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP

Semiconductor device

To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.

Signal generation circuit and temperature sensor

A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Semiconductor integrated circuit device

Device control method including: operation receiving step of receiving a device control operation for controlling a device; determining step of determining whether an operation terminal is in a first state or a second state; limiting step of, when determined in the determining step that the operation terminal is in the second state, limiting a range of controls of the device made available to the operation terminal when in the second state so as to correspond to part of a range of controls of the device made available to the operation terminal when in the first state; and device controlling step of controlling the device based on the device control operation. When determined in the determining step that the operation terminal is in the second state, the device is controlled within the range of controls of the device made available to the operation terminal when in the second state.

Device control method, device control system

The present invention provides a semiconductor device having a sensor capable of improving precision while suppressing increase in occupation area. A semiconductor device has: a first counter; and a second counter (time measuring circuit) measuring time until a count value, which is obtained by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the first counter. The first counter obtains a piece of digital information corresponding to the first voltage on the basis of a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, on the basis of the time measured by the time measuring circuit.

A device control method used in a device control system in which an operation terminal is used to remotely operate a device with a server device mediating between the operation terminal and the device, the device control method including: acquiring, upon reception of an operation instruction for operation of the device from the operation terminal, environment information pertaining to at least one of the device and the operation terminal; performing a determination of whether or not to cause execution of processing corresponding to the operation instruction based on whether or not the environment information satisfies a predetermined condition; and causing the device to execute an execution command for execution of the processing when a result of the determination is affirmative, and not causing the device to execute the execution command when the result of the determination is negative.

Device control method, device control system, and server device

A user-friendly cooperative process execution method for causing household electric devices that are registered to a server to execute cooperative processes. The server stores correspondence information associating a particular operation to be executed by a particular household electric device with one or more groups each composed of one or more household electric devices, and indicating, for each of the household electric devices in each of the groups, a control signal to be transmitted to the household electric device. The method includes: detecting whether or not the particular operation is executed; selecting one of the groups that is composed of one or more household electric devices that are registered to the server by referring to the correspondence information when the execution of the particular operation is detected; and transmitting the control signal to each of the household electric devices in the selected group.

Coordination processing execution method and coordination processing execution system

A server device () includes a first generation unit () generating binding information binding a user with content, a second acquisition unit () acquiring a usage rule, a second generation unit () generating a converted title key from a title key by using the binding information and the usage rule, and an output unit () outputting content encrypted using the title key, the converted title key and the usage rule to the storage medium (). A playback device () includes a generation unit () performing the reverse of the conversion on the converted title key of the storage medium () to generate a decrypted title key, by using the binding information received from the server device () and the usage rule of the storage medium (), and a decryption unit () decrypting the encrypted content of the storage medium () by using the title key.

Server device, playback device and content distribution system

A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.

Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array

Growing community of inventors

Tokyo, Japan

Masataka Minami