Kabushiki Kaisha Toshiba

Masataka Matsui

Yukihiro Urakawa

Kiyofumi Ochii

Takeo Maeda

Mitsuo Isobe

Hiroshi Momose

Takayuki Ohtani

Jun-ichi Tsujimoto

Hiroyuki Hara

Shigeyuki Hayakawa

Katsuhiko Sato

Azuma Suzuki

Takayuki Ootani

Tetsu Nagamatsu

Osamu Ozawa

Takahiro Hamano

Hiroshi Iwai

Yukihito Oowaki

Tadahiro Kuroda

Shinichiro Shiratake

Tohru Furuyama

Tomoaki Yabe

Tetsuya Fujita

Toshinari Takayanagi

Tetsuya Iizuka

Fumitoshi Hatori

Kazuhiko Hashimoto

Fumiyuki Yamane

Katsuhiro Seta

Yasuo Unekawa

Yukari Unno

Takayoshi Shimazawa

Syoichi Asoh

Kouichi Satou

According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

Semiconductor device and system

A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data. Since data written in the memory cell suffices to have a potential difference smaller than the potential difference between the power supply potential and the ground potential, the time required to drive the bit line having a large load capacitance is shortened, the power consumption is decreased, and the power consumption necessary for writing data in the memory cell is reduced.

Static random access memory including potential control means for

The disclosed semiconductor memory cell can be formed in accordance with the standard process for the logic LSI, so that the manufacturing cost can be reduced and an increased node capacitance can be secured. The drain diffusion layer (D1) of the latch transistor (M1) for constituting the latch of the memory cell is connected to a portion in the first metal layer through the contact (C1); the source diffusion layer (S1) of the latch transistor (M1) is the grounded wire connected to the first metal layer wire through the contacts (C3 and C3a); the poly silicon (P1) of the latch transistor (M1) is connected to the first metal layer wire or the second metal layer wire through the contact (C2); the first metal layer and the second metal layer are connected to each other by the through hole (V1) formed being overlapped with the contact (C3); the gate of the select transistor (M2) having the source connected to the drain diffusion layer (D1) of the latch transistor (M1) is connected to the word line (WL) of the poly silicon layer; the drain of the select transistor (M2) is connected to the first metal layer wiring through the contact (C4) and further connected to the bit lines formed in the second metal layer through the through hole (V2).

Semiconductor memory device composed of half cells

This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area.

Semiconductor memory device having two P-well layout structure

A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in the row direction of the input section and by reading out in the column direction of the input section, write section for selectively writing data into a first pair of memory cells of said corner turn memory array; and readout section for simultaneously reading data from a second pair of memory cells which are different from the first pair of memory cells.

Parallel-to-serial conversion device and linear transformation device

A first and second barrel shifters (BSA0 and BSA1) are connected directly without intervening any pipe-line register between the two, and a sense amplifier (R3A0) is provided at an output side of the second barrel register (BSA1). Further, the circuit patterns of the first and second barrel shifters are formed being overlapped with each other in such a way that the elements of one of the first and second barrel shifters are formed at the dead space of the other of the two barrel shifters to reduce the pattern area. In the shift circuit and the variable-length decoder, the data lines of the barrel shifters can be minimized in size and width.

Barrel shifter device and variable-length decoder

A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Semiconductor device having bipolar transistor and MOS transistor

In input transition detection pulse generators used in semiconductor memory devices, etc., in order to permit a designer to arbitrarily design the power supply voltage dependency of an output pulse width in accordance with use, a scheme is employed such that the functional block for detecting transition of an input or inputs to generate a pulse signal or signals, or the functional block for setting the width of each pulse signal is caused to have a function to generate pulse signals having different power supply voltage dependencies of pulse widths to perform a predetermined logical operation by a logical operation unit on the basis of pulse signals from the input transition detection pulse generation block or the pulse width setting block, thus to output a pulse having a pulse width optimum for a power supply voltage used. In place of the logical operation unit, an approach may be employed to select any one of a plurality of units as the input transition detection pulse generation block or the pulse width setting block by using a control signal to output a pulse having any pulse width. Further, the input transition pulse generation block or the pulse width setting block may be constructed to set at least one pulse width of pulses generated therefrom on the basis of a delay time generated by using an RC delay line.

Circuit for generating input transition detection pulse

A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Memory cell arranged in a matrix configuration are selected by a particular word line to supply the stored data to particular bit lines. The row address decoder selects a particular word line based on the address signal, while the column address decoder selects particular bit lines based on the address signal. Each of the row address decoder and column address decoder contains a first decoder for decoding the address signal, a delay circuit for delaying the output from the first decoder when data is written into the memory cell, and a second decoder for receiving the output signals from the first decoder and delay circuit and based on these signals, selecting either a particular word line or particular bit lines.

Static random access memory capable of preventing erroneous writing

A first threshold value for detecting a potential indicating a read state, and a second threshold value for detecting a write state are set in an inverter circuit, to which a read/write signal R/W for setting the state of a memory cell is supplied, by means of a P-channel transistor, an N-channel transistor, and another P-channel transistor which is much smaller in gate width than the above transistors. The first or second threshold value is selected by a logic circuit constituted by an inverter circuit and a delay circuit in accordance with the level of the read/write signal R/W. Therefore, a change from a read state to a write state and a reverse change can be detected at high speed, thus providing a read/write control circuit for a random access memory, which can increase the speed of a read operation immediately after a write operation while ensuring a sufficient data write time, and can shorten the write recovery time.

Read/write control device for random access memory

In a Bi-CMOS logic circuit in which a bipolar transistor and a CMOS element are formed on the same semiconductor substrate, a pull-down current of an output circuit is discharged through a MOS transistor having a large transconductance gm and a constant current source having a large current value. Thus, the speed of a pull-down operation is increased. Moreover, a constant current source need not be provided in an output circuit, and the MOS transistor is operated when it is required during a pull-down operation, thereby reducing an extra current. Therefore, a circuit having low power consumption can be obtained.

BiCMOS logic circuit with bipolar transistor and MOS transistor formed

A static memory device comprises a memory cell array having of a plurality of sections, each including a plurality of memory cells. A selection signal for selecting one section is generated in accordance with a data writing or reading operation. First and second potentials of high level are generated, and one of the potentials are selectively supplied to pairs of bit lines in one of the plurality of sections. In a data writing operation, the pairs of bit lines are precharged to the first potential, e.g., the supply voltage V.sub.cc, and in a data reading operation, the pair of bit lines is precharged to the second potential, e.g., V.sub.cc -2V.sub.f, where V.sub.f is a forward voltage of a diode.

Static memory device

A semiconductor device capable of performing a failure analysis includes a semiconductor substrate having a plurality of circuit elements, and an identification region provided above the semiconductor substrate so as to record identification information such as position information within wafers, information for wafer numbers, etc. The identification information is given by binary coded patterns, fused patterns of fuse elements, etc.

Semiconductor device having identification region for carrying out

According to this invention, there is provided a semiconductor static data memorizing apparatus including, a first power supply terminal, a second power supply terminal, a first TFT (thin film transistor), the first TFT having a first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a first data storage node for memorizing the second data, a second TFT, the TFT having the first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a second data storage node for memorizing the data, a third TFT, the third TFT having a second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the first data storage node, and a fourth TFT, the fourth TFT having the second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the second data storage node, wherein a gate of the first TFT is connected to the second memory node, and a gate of the second TFT is connected to the first data storage node, such that a flip-flip circuit is formed by the first power supply terminal, the second power supply terminal, the first TFT, the second TFT, the third TFT, and the fourth TFT, and further including data bit lines which are inverted with respect to each other, a first switching device for performing a switching operation between one of the bit lines and the first data storage node, a second switching device for performing a switching operation between the other of the data bit lines and the second data memory, and a word line device, connected to gates of the first and second switching devices, for controlling operations of the first and second switching devices.

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Tokyo, Japan

Masataka Matsui