Hitachi, Ltd.

Renesas Technology Corp.

Fujitsu Mobile Communications Limited

Mitsubishi Denki Kabushiki Kaisha

Solid State Storage Solutions LLC

Masataka Kato

Tetsuo Adachi

Hitoshi Kume

Toshihiro Tanaka

Katsutaka Kimura

Toshio Sasaki

Takashi Kobayashi

Toshiaki Nishimoto

Toshiyuki Mine

Nozomu Matsuzaki

Yoshimi Sudou

Shoji Shukuri

Yoshiaki Kamigaki

Shinichi Minami

Kozo Katayama

Osamu Tsuchiya

Kenji Kanamitsu

Keiichi Haraguchi

Toshiakl Nishimoto

Norio Suzuki

Kazuyoshi Oshima

Kazuyuki Miyazawa

Yasuyuki Nagashima

Tetsuya Tsujikawa

Masahito Takahashi

Teruko Fujii

Fukuo Owada

Akihiko Satoh

Yoshimasa Baba

Shiro Akamatsu

Hideo Miura

Tsuyoshi Kobayashi

Yoshinobu Nakagome

Yoshiaki Koizumi

Kenji Takahashi

Satoshi Meguro

Makoto Kawamura

Masaharu Kubo

Kazuhiro Komori

Wataru Matsumoto

Keiichi Yoshida

Hiroaki Kotani

Tohru Nakamura

Tsutomu Okazaki

Kazunori Furusawa

Takahiro Okabe

Kikuo Kusukawa

Kazuo Nakazato

Toshiya Uenishi

Katsunori Takami

Keisuke Ogura

Hideo Tobe

A disclosed portable apparatus includes: a first touch switch that is installed on a first surface of a housing of the portable apparatus; a second touch switch that is installed on a second surface of the housing, which is opposite to the first surface; and a determination unit configured to determine whether or not the first surface and the second surface are simultaneously touched, based on outputs of the first touch switch and the second touch switch. The portable apparatus may further include a first controller configured to release a lock function upon determining that the first surface and the second surface are simultaneously touched, and to activate the lock function upon determining that the first surface and the second surface are not simultaneously touched.

Portable apparatus and determination method

The portable terminal includes a display unit configured to display a screen; a first buffer and a second buffer configured to sequentially store display data for the displayed screen; a first determination unit configured to determine whether to perform single-buffer control or double-buffer control based on update data for the displayed screen; and a setting unit configured to set, if single-buffer control is appropriate, a display control method of the display unit to a display control method using the first buffer and to set, if double-buffer control is appropriate, a display control method of the display unit to a display control method using the first buffer and the second buffer.

Portable terminal

In one embodiment, a mobile communication terminal is equipped with a first control unit for execution a communication, a second control unit for executing an application program, and a timer unit for generating an interrupt signal when a count value equals a timer value set by the first control unit. The second control unit transmits first information including sleep time to the first control unit and changes to a sleep state. The first control unit sets a timer value in the timer unit in response to the first information and transmits to the second control unit second information for waking the second control unit when the interrupt signal is generated by the timer unit.

Mobile communication terminal

A mobile terminal includes a display unit configured to display a screen generated by combining plural screen layers, four controllers connected to the display unit; wherein a first controller determines whether a transmission specification of a subject screen layer to be updated is enabled upon updating of the screen, a second controller determines whether a size of the subject screen layer to be updated is equal to or larger than a size of a screen displayed by the display unit when the first controller determines 'YES', a third controller determines whether the screen layer to be combined on a back surface of the subject screen layer to be updated exists when the second controller determines 'YES'; and a fourth controller controls to disable the transmission specification of the subject screen layer to be updated when the third controller determines &#x201c;NO&#x201d;.

Mobile terminal

Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Nonvolatile semiconductor memory

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Nonvolatile semiconductor memory device and a method of the same

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

Semiconductor integrated circuit having discrete trap type memory cells

A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistor; is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.

Nonvolatile semiconductor memory device

Growing community of inventors

Koganei, Japan

Masataka Kato