Sumco Corporation

Sumitomo Mitsubishi Silicon Corporation

Sumitomo Sitix Corporation

Sumitomo Metal Industries, Inc.

Niigata University

Masataka Hourai

Toshiaki Ono

Wataru Sugimura

Shigeru Umeno

Shinsuke Sadamitsu

Tadami Tanaka

Eiji Kajita

Kazunari Kurita

Yasuo Koike

Takayuki Kihara

Nobumitsu Takase

Eiichi Asayama

Manabu Nishimoto

Toshiyuki Fujiwara

Kiyoshi Nagai

Hiroyuki Takao

Shuichi Samata

Noritomo Mitsugi

Hiroshi Kaneta

Yuichi Nemoto

Kei Matsumoto

Ryuji Ohno

Terutaka Goto

Masanori Akatsuka

Shinichiro Miki

Shin Uchino

Masakazu Sano

Hiroshi c/o Niigata University Kaneta

Provided is a method of producing a high resistance n-type silicon single crystal ingot with small tolerance margin on resistivity in the crystal growth direction, which is suitably used in a power device. In the method of producing a silicon single crystal ingot using Sb or As as an n-type dopant, while a silicon single crystal ingot is pulled up, the amount of the n-type dopant being evaporated from a silicon melt per unit solidification ratio is kept within a target evaporation amount range per unit solidification ratio by controlling one or more pulling condition values including at least one of the pressure in a chamber, the flow volume of Ar gas, and a gap between a guide portion and the silicon melt.

Method of producing silicon single crystal ingot and silicon single crystal ingot

A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.

Silicon wafer and method for manufacturing the same

In this silicon single crystal wafer for IGBT, COP defects and dislocation clusters are eliminated from the entire region in the radial direction of the crystal, the interstitial oxygen concentration is 8.5&#xd7;10atoms/cmor less, and variation in resistivity within the wafer surface is 5% or less. This method for manufacturing a silicon single crystal wafer for IGBT includes introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5&#xd7;10atoms/cmor less at a silicon single crystal pulling speed enabling pulling of a silicon single crystal free of grown-in defects. The pulled silicon single crystal is irradiated with neutrons so as to dope with phosphorous; or an n-type dopant is added to the silicon melt; or phosphorous is added to the silicon melt so that the phosphorous concentration in the silicon single crystal is 2.9&#xd7;10to 2.9&#xd7;10atoms/cmand a p-type dopant having a segregation coefficient smaller than that of the phosphorous is added to the silicon melt so that the concentration in the silicon single crystals is 1&#xd7;10to 1&#xd7;10atoms/cmcorresponding to the segregation coefficient thereof.

Silicon single crystal wafer for IGBT and method for manufacturing silicon single crystal wafer for IGBT

A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0&#xd7;10atoms/cmand with a diameter of a COP occurring region not more than a diameter of a crystal, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, and mirror polishing the other main surface of the wafer.

Silicon wafer and method for producing the same

A method of evaluating a silicon wafer includes obtaining first surface distribution information indicating an surface distribution of photoluminescence intensity on a surface of a silicon wafer; after obtaining the first surface distribution information, subjecting the silicon wafer to a thermal oxidation treatment, and then obtaining second surface distribution information indicating an surface distribution of photoluminescence intensity on the surface of the silicon wafer; obtaining difference information for the first surface distribution information and third surface distribution information, with the third surface distribution information having been obtained by correcting the second surface distribution information with a correction coefficient of less than 1; and based on the difference information obtained, evaluating an evaluation item selected from the group consisting of absence or presence of oxygen precipitates and surface distribution of oxygen precipitates in the silicon wafer being evaluated.

Method of evaluating silicon wafer and method of manufacturing silicon wafer

Disclosed are high resistivity silicon wafers, wherein the interstitial oxygen concentration thereof is 8&#xd7;10atoms/cm(ASTM F121-1979) or less, BMD (Bulk Micro Defect) density&#x2014;oxygen precipitate within wafer&#x2014;is 5&#xd7;10pieces/cmor less, and an electric resistivity thereof is 100 &#x3a9;&#xb7;cm or more. And further disclosed are high resistivity silicon wafers having an electric resistivity of 100 &#x3a9;&#xb7;cm or more, which are cut from crystal region where no COP (Crystal Originated Particle) exist, and in which neither COP (Crystal Originated Particle) nor oxygen precipitate exist at the area from wafer surface to the depth of 5 &#x3bc;m or more owing to high temperature treatment. It is preferable that, in said high resistivity wafers, carbon concentration in wafers is 1&#xd7;10atoms/cmor more (ASTM F123-1981), and/or nitrogen concentration is 1&#xd7;10atoms/cmor more. Accordingly, high resistivity silicon wafers are provided, wherein the mechanical strength thereof is highly secured, and an excellent characteristic to slip generation is provided, so as to be optimal for base wafers of silicon wafers having a SOI structure or an epitaxial structure.

High resistivity silicon wafers

To provide a method of removing a heavy metal contained in a thinned semiconductor substrate. A method of removing a heavy metal in a semiconductor substrate of the present invention comprises: attaching, to a rear surface of the semiconductor substrate, a material that lowers a potential barrier of the rear surface of the semiconductor substrate, on a front surface of which a circuit is to be formed or is formed; applying a thermal treatment to the semiconductor substrate under a condition based on a thickness and a resistivity of the semiconductor substrate; and, depositing the heavy metal in the semiconductor substrate on the rear surface.

Method of removing heavy metal in semiconductor substrate

There is provided a quantitative evaluation device or the like of atomic vacancy existing in a silicon wafer in which the atomic vacancy concentration in the silicon wafer can be quantitatively evaluated by forming a rationalized thin-film transducer on a surface of a silicon sample without conducting an acceleration treatment for enhancing the concentration. This is characterized by comprising a magnetic force generating meansfor applying an external magnetic field to a silicon samplecut out from a given site of a silicon wafer, a temperature controlling meanscapable of cooling the silicon sampleto a temperature region of not higher than 50 K, a ultrasonic oscillating-detecting meansfor oscillating ultrasonic pulse to the surface of the silicon sampleand propagating the oscillated ultrasonic pulse into the silicon sampleand detecting a change of sound velocity in the propagated ultrasonic pulse, wherein a thin-film transducerhaving properties capable of following to an expansion of the silicon sampleat the above temperature region and substantially aligning C-axis in a given direction is directly formed on the surface of the silicon sample

Quantitative evaluation device and method of atomic vacancy existing in silicon wafer

A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90&#xb0; light scattering method is formed in a region at a depth from the wafer surface of 25 &#x3bc;m or more but less than 100 &#x3bc;m, and a layer which has a light scattering defect density of 1&#xd7;10/cmor more according to the 90&#xb0; light scattering method is formed in a region at a depth of 100 &#x3bc;m from the wafer surface.

Silicon wafer and its manufacturing method

By using oxygen-containing silicon wafers obtained by the CZ method and by combining the first heat treatment comprising controlled heat-up operation (ramping) with the second heat treatment comprising high-temperature heat treatment and medium temperature heat treatment in accordance with the process for producing high-resistance silicon wafers according to the present invention, it is possible to obtain high-resistance silicon wafers capable of maintaining their high resistance even after heat treatment in the process of device manufacture while efficiently inhibiting the formation of oxygen donors and preventing changes in resistivity. Further, excellent epitaxial wafers and SOI wafers can be produced using those high-resistance silicon wafers and, therefore, they can be applied in a wide field including high-frequency communication devices and analog/digital hybrid devices, among others.

Process for producing high-resistance silicon wafers and process for producing epitaxial wafers and SOI wafers

When growing a silicon single crystal free of grown-in defects based on the CZ method, the crystal is pulled out at a critical pulling rate at which a ring-shaped OSF occurrence region vanishes in a center portion of the crystal by using a hot zone structure in which a temperature gradient Gc in a center portion of the crystal is equal to or greater than a temperature gradient Ge in a peripheral portion of the crystal, while supplying an inert gas including hydrogen to an interior of a pulling furnace. The critical pulling rate at which the ring-shaped OSF occurrence region vanishes in the center portion of the crystal is increased, and single crystals free of grown-in defects in which dislocation clusters and COPs can be grown by pulling at a pulling rate higher than that of the prior art.

Silicon wafer, SOI substrate, method for growing silicon single crystal, method for manufacturing silicon wafer, and method for manufacturing SOI substrate

There is obtained a silicon wafer which has a large diameter, where no slip generated therein in a wide range of a density of oxygen precipitates even though a heat treatment such as SLA or FLA is applied thereto, and which has high strength. First, by inputting as input parameters combinations of a plurality of types of oxygen concentrations and thermal histories set for manufacture of a silicon wafer, a Fokker-Planck equation is solved to calculate each of a diagonal length L and a density D of oxygen precipitates in the wafer after a heat treatment step to form the oxygen precipitates () and immediately before a heat treatment step of a device manufacturing process is calculated. Then, a maximum heat stress S acting in a tangent line direction of an outer peripheral portion of the wafer in the heat treatment step of the device manufacturing process is calculated based on a heat treatment furnace structure and a heat treatment temperature used in the heat treatment step of the device manufacturing process, and then an oxygen concentration or the like satisfying the following Expression (1) is determined:12000&#xd7;&#x2003;&#x2003;(1).

Method for manufacturing silicon wafer method

A silicon single crystal is grown by the CZ method. A silicon melt from which the crystal is grown is added with dopant such that the crystal has a resistivity of 0.025 to 0.08 &#x3a9;cm. As well as the dopant, carbon is added to the silicon melt. The crystal is pulled in a hydrogen-bearing inert atmosphere.

Silicon wafer, method for producing silicon wafer and method for growing silicon single crystal

An active layer side silicon wafer is heat-treated in an oxidizing atmosphere to thereby form a buried oxide film therein. The active layer side silicon wafer is then bonded to a supporting side wafer with said buried oxide film interposed therebetween thus to fabricate an SOI wafer. Said oxidizing heat treatment is carried out under a condition satisfying the following formula:[]&#x2266;2.123&#xd7;10exp(&#x2212;(+273)),where, T is a temperature of the heat treatment, and [Oi] (atmos/cm) is an interstitial oxygen concentration.

Growing community of inventors

Tokyo, Japan

Masataka Hourai