Mitsubishi Denki Kabushiki Kaisha

Renesas Technology America, Inc.

Masashige Tada

Takehiko Umeyama

Robert Ross

Magneto-resistive (MR) head pre-amplifiers for single polarity power supply applications are presented. An exemplary pre-amplifier includes a bias network coupled to first and second input terminals of the pre-amplifier, the input terminals for receiving signals corresponding to variations in magnetic fields from an MR head. At least one gain stage having first and second input terminals and first and second output terminals for amplifying the received signals is included. A pair of coupling capacitors, each capacitor being connected between a respective input terminal of the pre-amplifier and a corresponding respective input terminal of the at least one gain stage, are further included in the pre-amplifier design. Finally, the exemplary pre-amplifier includes a pair of feedback capacitors, each capacitor being connected between respective input and output terminals of the at least one gain stage. The pre-amplifier is powered by a single polarity power supply.

Differential magneto-resistive head pre-amplifiers for single polarity power supply applications

A MR head amplifier of the present invention prevents a base potential of a transistor which supplies a current to a MR element from changing in a moment when the MR element changes from a write-state to a read-state. The MR head amplifier includes a loop amplifier that has a non-inverted input terminal connected to one end of a first transistor which supplies a current to a MR element and an inverted input terminal connected to one end of a second transistor which is supplied with a constant current through a constant current source. An output terminal of the loop amplifier is feedback to a base terminal of the first transistor via a first switch and one end of a capacitor whose other end is connected to a ground is connected to an output terminal of the first switch. The loop amplifier includes a second switch connected between the output terminal of the first switch and the base terminal of the first transistor, the second switch being closed during read-state and opened during write-state.

Amplifier with capacitive feedback for driving a magneto-resistive head

A charge pump with which a dynamic range of control voltage can be set broadly and a phase locked loop using the charge pump. The charge pump includes first, second and third transistors having respective first terminals for supplying constant currents to an output terminal. A second terminal of the first transistor is connected through a resistor to a power source. Second terminals of the second and third transistors are grounded through respective first and second T/M circuits (transmission gate analog switch circuits). A DOWN signal is applied to the first T/M circuit, and an inverted UP signal is applied to the second T/M circuit, in order to supply or draw out current via the output terminal.

Charge pump circuit and phase locked loop circuit using the charge pump

In a charge pumping circuit capable of setting a wide output voltage range, a current mirror circuit (4) is provided with a transistor (T5) having an emitter which is grounded through a resistance (R1) and a collector (base) which is connected to that of a transistor (T2), and a transistor (T6) having an emitter which is grounded through a resistance (R2), and a collector which is connected to an output terminal (3). The transistor (T2) has a base which receives an inverted down signal/DOWN, and an emitter which is connected to a constant current source (1). A current mirror circuit (5) is provided with a transistor (T7) having an emitter which is connected to a power source (VDD) through a resistance (R3) and a collector (base) which is connected to that of a transistor (T4), and a transistor (T8) having an emitter which is connected to the power source (VDD) through the resistance (R2) and a collector which is connected to the output terminal (3). The transistor (T4) further has a base which receives an up signal (UP), and an emitter which is connected to the constant current source (2).

Charge pumping circuit and PLL circuit

An integrated circuit (IC 101) has ECL circuits (E3 to En). Bias current (I3) applied to the ECL circuit (E3) is fed by a current mirror circuit consisting of transistors (Q3 and Q1) and resistors (R2 and R3). Constant current (IO) flows in the transistor (Q1) by a constant current circuit (4). The transistor (Q1) has its collector connected to one end of a resistor (R1), the other end of which is connected to a test terminal (2). With an outside resistor (Rb) connected to the test terminal (2) of the integrated circuit (IC 101), part of the constant current (IO) is pulled out to the outside, and the current flowing in the resistor (R2) becomes small. Accordingly, the bias current (I3) is reduced. A voltage difference .DELTA.V of logic states in the ECL circuit (E3) can be controlled from the outside without controlling a temperature, and a test of an inferior transistor the ECL circuit (E3) has can be performed.

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Tokyo, Japan

Masashige Tada