Fujitsu Corporation

Fujitsu Semiconductor Limited

Masashi Yamawaki

Kenichi Yamakura

Hirofumi Yamawaki

Yoshitaka Kitamura

When a still picture is picked up by a digital camera, the still picture is divided into a plurality of areas and is processed for each area. After the process of one divided area is completed, then the process of a motion picture obtained from an imaging device. After the process of the motion picture is completed, another divided area of the still picture is processed again. Such switching between a motion picture process and a still picture process is performed until the process of the entire still picture is completed. Thus, after a still picture is picked up by a digital camera, a motion picture can be promptly displayed and a live image picked up by the camera can be displayed on a back LCD screen.

Image processing device for inputting both still picture data and motion picture data and performing a data process

A data writing device for preventing a phase-change optical disc from deteriorating due to repeated writing and for preventing the rewritable number of times of the disc from decreasing. The device writes data including synchronization frames to the disc. Each synchronization frame includes a primary or secondary synchronization signal. A comparator compares a first accumulated DSV for specifying the data including the primary synchronization signal for the synchronization frame with a second accumulated DSV for specifying the recording data including the secondary synchronization signal for the synchronization frame and generates a first selection signal based on the comparison. An inverter randomly inverts the first selection signal to generate a second selection signal. A selection circuit receives the primary and secondary synchronization signals and outputs the primary or secondary synchronization signal in response to the second selection signal.

Device and method for writing data

In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Data processor and data processing method

A delay circuit is constructed by connecting taps TAP&#x2013;n for providing with a unit delay time (&#x3c4;) in series on multiple stages. Each tap has the same configuration and an objective signal is inputted to a signal input terminal IN. The output terminal of a preceding stage tap is connected to a between-stages connecting terminal IN. An output terminal O is connected to the between-stages connecting terminal of a next stage tap. The signal input terminal and the between-stages connecting terminal are connected to one input terminal of NAND gatesand a tap selection signal is inputted to the other input terminal. The output terminal is connected to a NAND gate. One of the NAND gatesfunctions as a logical inversion gate corresponding to a tap selection signal so as to enable propagation of the signal. At this time, in the other NAND gate, the output signal is fixed to high level and the NAND gatealso functions as a logical inversion gate. The objective signal is propagated by the NAND gatesand the preceding stage signal is propagated by the NAND gates. By constructing the NAND gateswith the same structure, the unit delay time (&#x3c4;) can be matched accurately.

Delay circuit and control method of the delay circuit

An apparatus for writing block data, which includes a plurality of sectors, to a recording medium. The apparatus includes a controller for generating the block data and writing the block data to the recording medium. The controller performs a padding process on final block data when the final block data is written to the recording medium. The controller includes a padding processing unit for generating padding process data. The generation of the padding process data with the controller reduces the load of a processing unit that controls the controller.

Apparatus for writing data and method for generating DVD format data

A real-time recording system that decreases the load applied to a central processing unit, which controls recording. The recording system includes a memory for storing input data. An error correction circuit is connected to the memory for generating write data from the input data and storing the generated write data in the memory. A formatter circuit is connected to the memory and the error correction circuit for reading the write data stored in the memory and writing the read write data to the recording medium in real-time. The error correction and formatter circuits are controlled for the generation of the write data with the error correction circuit and the writing operation with the formatter circuit by a plurality of control signals. The control signals are transferred between the error correction circuit and the formatter circuit.

Real-time recording system and real-time recording method

In an information access device, an information access method and an information storage medium access system which are suited to quickly and reliably detect a deviation in frame management associated with erroneous detection of a synchronous mark and to perform an operation of redetecting a synchronous mark, an Even synchronous mark erroneous detector outputs a count-up signal if a synchronous mark LSY from an LPP pattern comparing portion is &ldquo;111&rdquo; when an Even/Odd identification signal from a frame counter assumes 1. An Odd synchronous mark erroneous detector outputs a count-up signal if the synchronous mark LSY is &ldquo;110&rdquo; when the Even/Odd identification signal assumes 0. An erroneous detection counter counts the number of the outputted count-up signals, which is compared with a count value set by a redetection level portion in a comparator. Then a redetection instruction signal for redetecting an LPP access synchronous mark is outputted.

Information access device, information access method, and information storage medium access system

An error correcting method reducing the time needed to provide error correction using a buffer memory. The method includes performing row error correction by using a plurality of rows of data to produce row-corrected block data and performing column error correction by using the plurality of columns of data to produce column-corrected block data. In addition, at least one of the performing row error correction and performing column error correction operates using a plurality of rows or columns of data in units of a predetermined number of rows or columns so as to provide error correction for the plurality of rows or columns in parallel.

Method and apparatus for correcting data errors

A descrambling method is suitable for improving the data transfer rate and fast data processing separate scrambled data into a plurality of data groups each including plural pieces of scrambled unit data. Initial scramble patterns are respectively assigned to the data groups. An initial scramble pattern is prepared and assigned to a specific data group. A first scramble pattern is generated in one clock cycle using the prepared initial scramble pattern and then one of the scrambled unit data pieces in the specific data group is prepared. A descrambling operation using the first scramble pattern and the prepared one scrambled unit data piece is then performed to produce an original data piece.

Method of descrambling scrambled data using a scramble pattern and

A disk apparatus for reproducing pulse width modulation (PWM) data from a disk is disclosed. A first sync pattern detector compares data DTLE with a first sync pattern. A second sync pattern detector compares data DTTE with a second sync pattern. A first signal generator stops the detecting operation of the first detector when the first detector has detected the first sync pattern from the data DTLE. A second signal generator stops the detecting operation of the second detector when the second detector has detected the second sync pattern from the data DTTE. A first time check circuit restarts the detecting operation of the first detector when the first sync pattern has been detected first and the second sync pattern is not detected within a predetermined period of time. A second time check circuit restarts the detecting operation of the second detector when the second sync pattern has been detected first and the first sync pattern is not detected within a predetermined period of time.

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Kasugai, Japan

Masashi Yamawaki