Toshiba Memory Corporation

Kioxia Corporation

Masashi Yamaoka

Noriyasu Kumazaki

Junichi Sato

Akio Sugahara

Norichika Asaoka

Yuzuru Shibazaki

Kazuto Uehara

Takaya Handa

Yuri Terada

Bushnaq Sanad

Ryosuke Isomura

Sanad Bushnaq

Naoki Yamamoto

Kazuhiro Tomishige

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Memory device which generates operation voltages in parallel with reception of an address

According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Semiconductor storage device

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other. When a distance between the first conductive layer and the second conductive layer in the first direction is a first distance, a distance between the third conductive layer and the fourth conductive layer in the first direction is a second distance, and a distance between the fifth conductive layer and the sixth conductive layer in the first direction is a third distance, the second distance is smaller than the first distance, and the third distance is smaller than the second distance.

A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

According to an embodiment, a semiconductor memory device includes first and second groups each including a plurality of memory cells, and a control circuit. The control circuit is configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a memory cell in the first or second group, and to apply a third voltage to the memory cell after applying the second voltage. When the memory cell is included in the first group, the control circuit applies the third voltage to the memory cell a time earlier with respect to a time when the second voltage is applied than when the memory cell is included in the second group. Each of the first and second groups corresponds to a data erase unit or a unit larger than the data erase unit.

Semiconductor memory device

According to one embodiment, a semiconductor memory includes: a memory cell array provided in a first layer above a semiconductor substrate and including a plurality of memory cells; a first word line coupled to a first memory cell of the plurality of memory cells; a driver generating a voltage applied to the first word line; a first transistor including one end coupled to the first word line and the other end coupled to the driver; a first transfer gate line coupled to a gate of the first transistor and including a portion passing through the first layer, a second layer between the semiconductor substrate and the first layer, and a third layer above the first layer; and a first level shifter applying a voltage to the first transfer gate line.

Semiconductor memory including plural memory blocks, a sequencer that controls a driver, a row decoder, and sense amplifier modules based on commands held in a command register to perform read, write, erase

A semiconductor memory device includes first and second memory cells, first and second word lines that are connected to the first and second memory cells, respectively, a first transistor connected to one end of the first word line, and second and third transistors respectively connected to first and second ends of the second word line. During a read operation on the first and second memory cells, when the first word line is selected, a first voltage is applied to the second word line, and then a second voltage is applied to the first word line, and when the second word line is selected, the first voltage is applied to the first word line, and then the second voltage is applied to the second word line. The second voltage is applied to the first word line for a longer duration than is applied to the second word line.

Growing community of inventors

Yokohama Kanagawa, Japan

Masashi Yamaoka