Hitachi, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Mitsubishi Denki Kabushiki Kaisha

Hitachi Ulsi Engineering Corp.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Honda Motor Co., Ltd.

Mitsubishi Electric Corporation

Akita Electronics Co., Ltd.

Masashi Wada

Akinori Matsuo

Takeshi Furuno

Yoshiki Kawajiri

Masashi Watanabe

Masahito Takahashi

Yoshiharu Nagayama

Kazuo Naito

Michio Fujimoto

Toshihiro Tanaka

Shinichi Kobayashi

Yutaka Shinagawa

Masamichi Fujito

Takashi Yamaki

Kazufumi Suzukawa

Kazunori Furusawa

Shinji Kawai

Kiichi Makuta

Takao Okubo

Kazuki Honma

Michiko Odagiri

Hirofumi Sonoyama

Takeshi Wada

Yasuhiro Nakamura

Kihachiro Tanaka

Taichi Sato

Masayuki Otsuka

Yoshiharu Mohri

Mikio Sugawara

Toshiyuki Tanaka

Tomohiro Takahashi

Hiroshi Sato

Yasuhiko Taito

Naoki Inoue

Yukihiro Homma

Yuta Ikeda

Takao Honmei

Tadashi Omae

Motoharu Ishii

Hiroshi Osakada

Kenji Kozakai

Makoto Oi

Yosuke Yoshizawa

Takao Okuba

Takao Hommei

Takeshi Nakamura

Shuichi Kuwahara

Jun Eto

A rectenna device includes an antenna (), a first rectifier () to rectify a radio frequency wave input in the antenna (), an antenna (), a second rectifier () to rectify a radio frequency wave input in the antenna (), and a capacitive coupler () to form an open circuit in response to direct current and to form a short circuit in response to a fundamental wave. The first rectifier () includes a ground (GND) conductor () to be a reference potential, and the second rectifier () includes a GND conductor () to be a reference potential. The GND conductor () and the GND conductor () are connected with the capacitive coupler () in between. The first rectifier () and the second rectifier () are connected in series.

Rectenna device

A fuel cell stack includes a stack body formed by stacking a plurality of power generation cells. A first seal line of a first metal separator and a second seal line of a second metal separator protrude in a stacking direction of the stack body in a manner to contact a resin film. An insulator is provided with a first elastic seal member which contacts a second end seal line. The width of the first elastic seal member is larger than the maximum width of the second end seal line.

Fuel cell stack

Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic '1' (or logic '0'), writing operation to bits corresponding to write data having the logic &#x201c;0&#x201d; (or logic &#x201c;1) is successively performed.

Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory

Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.

Semiconductor device and method of the semiconductor device

A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

Semiconductor memory, memory device, and memory card

Semiconductor device in which a chip is supplied either a first voltage or a second voltage

The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.

Semiconductor memory device

Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic &ldquo;1&rdquo; (or logic &ldquo;0&rdquo;), writing operation to bits corresponding to write data having the logic &ldquo;0&rdquo; (or logic &ldquo;1) is successively performed.

Nonvolatile memory, semiconductor device and method of programming to nonvolatile memory

The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage V generated by a reference voltage generating section and the detection voltage obtained by dividing a supply voltage V by means of resistors and and outputs it as a detection signal K. The reference voltage generating section generates reference voltage V from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage V can be minimized.

Semiconductor integrated circuit device having reference voltage generating section

A semiconductor memory ( ) comprising a plurality of memory blocks ( and ) provided with a lot of memory cells, a data input/output buffer ( ), and first control means ( ) for controlling the rewriting and reading of data for the memory cells is provided with first storage means ( ) for designating part of the defective memory blocks and detection means ( ) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

A semiconductor memory (,) comprising a plurality of memory blocks (,and,) provided with a lot of memory cells, a data-input/output buffer (,), and first control means (,) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (,) for designating part of the defective memory blocks and detection means (,) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltages, or is provided with an automatic erasing circuit for executing these operations.

Batch erasable single chip nonvolatile memory device and erasing method

It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.

Nonvolatile semiconductor memory device having data line dedicated to

Growing community of inventors

Kodaira, Japan

Masashi Wada