Nec Electronics Corporation

Nec Corporation

Renesas Electronics Corporation

Masashi Tsubota

Kimitake Tsuyuno

Tomoya Katsuki

An angle error correction device includes an actual rotation angle measurement circuit that converts a rotation angle information of a rotation angle detection target to an angle counter value for each predetermined angle; an actual speed calculator that calculates an actual rotation speed for each predetermined angle from the angle counter value; a curve interpolation circuit that generates a curve interpolation equation from the angle counter value; an ideal speed estimator that calculates an estimated ideal rotation speed for each predetermined angle using the curve interpolation equation; an angle error detector that calculates an angle error for each predetermined angle by integrating an angle ripple ratio determined by the actual rotation speed and the estimated ideal rotation speed; an angle error table in which the angle error calculated by the angle error detector is stored; and a correction circuit that corrects the rotation angle information using the angle error table.

Angle error correction device

To solve the problem of multi-pulse control in which the load of the control software is increased and further switching/timing adjustment is required, a semiconductor device includes a control unit including a CPU and a memory, a PWM output circuit for controlling the driver IC to drive the power semiconductor device, a current detection circuit for detecting the motor current, and an angle detection circuit for detecting the angle of the motor. The PWM output circuit includes a square wave generator circuit to generate a square wave based on the angle of the angle detection circuit as well as the base square wave information.

Semiconductor device and power conversion device

In an embodiment of the invention, if a microprocessor detects runaway of a CPU executing a program, it starts a recovery program. The runaway in the program execution is detected by monitoring accesses a non-implementation space in a program space. If the CPU accesses any address in the non-implementation space, the microprocessor sends an instruction to the CPU to execute a predetermined recovery program. Thereby, the microprocessor can detect and stop the runaway into the non-implementation space.

Semiconductor circuit device and method of detecting runaway

A PWM signal generation of the present invention includes a counter, a compare register, a comparator comparing a compare value of the compare register with a count value of the counter and outputting an identity signal, a PWM signal generation circuit determining a pulse width of a PWM signal according to the identity signal, and an additional bit setting register storing an additional bit provided to change the pulse width of the PWM signal.

PWM signal generation apparatus and method thereof and motor control apparatus and method thereof

A motor control apparatus for controlling a motor based on an output from a sensor includes a storage unit storing a value according to an excitation power supply to excite the sensor, a PWM output unit outputting a PWM output signal having a pulse width modulated to have a duty ratio corresponding to a value stored to the storage unit, and a filter input with the PWM output signal from the PWM output unit. The sensor is supplied with the excitation power supply based on an output from the filter.

Motor control apparatus, motor control circuit, and method thereof

In a method of generating pulse-width modulated waveform, the cycle of a carrier wave for the waveform is determined together with a first dead time value and a second dead time value both of which are set in a plurality of up-down counters, respectively. Using the plurality of the up-down counters is effective to assign individual dead times to upper and lower arms and to linearly control a PWM duty from 0% to 100%.

Method and apparatus for generating pulse-width modulated waveform

There is provided a micro-processor including (a) a pre-fetch cue FIFO which fetches and stores therein a command code, (b) a pre-fetch cue valid indicating that an effective command code is stored in the pre-fetch cue FIFO, (c) an access priority judging circuit receiving a pre-fetch request signal indicating that there is vacancy in the pre-fetch cue FIFO, a cue empty signal indicating that the pre-fetch cue FIFO is entirely empty, and an operand data request signal indicating that there has been generated an operand data access, and determining a kind of next bus access, (d) a bus state control circuit transmitting a bus interface signal, based on the kind of next bus access having been determined by the access priority judging circuit, and also transmitting a burst transfer signal indicating that a memory is in a condition for carrying out burst transfer, and (e) an access register storing data about the previous bus access. The access priority judging circuit takes a command fetch access in preference to an operand data access in the next bus access when data stored in the access register is a command fetch access, and the pre-fetch request signal, the operand data request signal, and the burst transfer signal are all transmitted.

Micro-processor

A microprocessor which has bus cycles of a memory access operation, an I/O access operation, and an idle state, includes a register for storing the number of the idle states to be inserted when first and second I/O accesses are consecutively executed, and a counter circuit for counting a clock when the first I/O access has been executed. A resetting circuit receives a signal indicating that the last access is the I/O access and resets the counter circuit when the first I/O access has been executed, and a comparator compares an output of the register with an output of the counter circuit for generating a recovery end signal when coincidence is detected. A timing generator generates state signals to the effect that the second I/O access is not executed until the recovery end signal is generated. With the inventive configuration, in the case of consecutive I/O accesses, after completion of a first I/O access, the idle state, in which no bus access is executed, is repeatedly inserted, with the number of idle states being inserted being counted by the counting circuit. The number of repeated idle states counted by the counting circuit is compared with the value stored in the memory and, when coincidence is detected, the recovery end signal is outputted so that a next I/O access is started.

Microprocessor capable of ensuring flexible recovery time for I/O device

A status register apparatus includes a control information register for holding one item of control information. An ON decoder is connected to receive a control word composed of a plurality of bits and for generating a set signal to the control information register when the ON decoder detects a first bit pattern for setting the control information register into an on condition. An OFF decoder is connected to receive the control word and for generating a clear signal to the control information register when the OFF decoder detects a second bit pattern for setting the control information register into an off condition. When the first bit pattern is detected by the ON decoder, the control information register is set to the on condition in response to the set signal. When the second bit pattern is detected by the OFF decoder, the control information register is set to the off condition in response to the clear signal. When neither the first bit pattern nor the second bit pattern is detected, the control information register maintains its preceding condition.

Microprocessor status register having plural control information

An address translation system for converting into a real address a virtual address including a virtual section number, a virtual area number and a virtual page number, comprises a plurality of stages of tables including at least area tables and page tables, a translation look-aside buffer having a plurality of entries each storing a virtual section number, a virtual area number and a virtual page number, an area preservation register for preserving a virtual section number and a virtual area number of a given virtual address when a new entry is registered into the translation look-aside buffer, a table register for preserving an output of an area table selected when the new entry is registered into the translation look-aside buffer, and an area comparator for comparing a content of the area preservation register with a virtual section number and a virtual area number of a given virtual address. When the translation look-aside buffer is retrieved on the basis of the given virtual address, if an entry having the same virtual section number, virtual area number and virtual page number as those of the given virtual address is not found, the area comparator is used for comparing the content of the area preservation register with the virtual section number and the virtual area number of the given virtual address. If coincidence is detected by the comparator, an address translation is performed by accessing a page table on the basis of the page table information preserved in the page table register, without accessing the area table.

Address translation system with register storing section and area numbers

A microprocessor according to the present invention is established in either data processing or monitoring mode of operation, and an address code and a data code produced by itself in the monitoring mode of operation are compared with corresponding address and data codes supplied from another microprocessor in the data processing mode of operation so as to decide whether or not aforementioned another microprocessor performs without any troubles, wherein address and data comparator units of the microprocessor respectively produce an address matching signal and a data matching signals upon respective coincidences between the address and data codes and the corresponding address and data codes, however, a delay unit retards the address matching signal by a predetermined time period in a pipeline bus cycle so as to match the address matching signal with the data matching signal.

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Kanagawa, Japan

Masashi Tsubota