Mitsubishi Electric Corporation

Kabushiki Kaisha Yakult Honsha

Masashi Sakai

Satoshi Kudo

Hideyuki Yamatoya

Yoichiro Mitani

Takuma Mizobe

Yasuhiro Kimura

Akihito Ohno

Takuyo Nakamura

Naomi Mizusawa

Takahiro Yamamoto

Kazuo Kobayashi

Keita Takahashi

Nobuyuki Tomita

Koji Nakajima

Yasunari Hino

Kenichi Hamano

Takashi Kanazawa

Shusuke Hashimoto

Kazuki Sakata

Mamoru Takikita

Teruo Yokokura

Takuto Yano

Kosuke Nakano

Kazutoshi Awane

Masayoshi Tamura

Takao Mitsui

Yoshiyuki Deguchi

Tomoyuki Sako

Tsunekazu Watanabe

Kisaku Shimura

Yoshiyuki Shishido

Shinichiro Katsuki

Tsuneo Matsumoto

Osamu Matsuo

Hiroshi Sansawa

Masaharu Onoue

Rika Ebina

Provided are a silicon carbide epitaxial growth device capable of fostering epitaxial growth on a silicon carbide substrate. Mounting a wafer holder loaded with a silicon carbide substrate and a tantalum carbide member to a turntable in a susceptor, and supplying a growth gas, a doping gas, and a carrier gas into the susceptor by heating by induction heating coils placed around the susceptor, thereby epitaxial growth is fostered, and stable and proper device characteristics are obtained, moreover, the yield in a manufacturing step of the silicon carbide epitaxial wafer is significantly improved.

Silicon carbide epitaxial growth device and method of manufacturing silicon carbide epitaxial wafer

Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including Hgas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T, the second temperature T, and the third temperature Tsatisfy T>T>T.

Method of manufacturing silicon carbide epitaxial wafer

This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.

Semiconductor device and semiconductor module using same

A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5&#xd7;10/cmor more and 2&#xd7;10/cmor less.

SiC epitaxial wafer, semiconductor device, and power converter

The object is to provide a technique for enabling determination of an appropriate test condition. A test condition determining apparatus includes a map generating unit, a withstand voltage estimating unit, and a test condition determining unit. The map generating unit generates a wafer map relevant to a plurality of chips, based on measurement values of thicknesses and carrier concentrations of an epitaxial growth layer, and measurement results of crystal defects in the epitaxial growth layer and a substrate. The withstand voltage estimating unit estimates a withstand voltage of each of the chips based on the wafer map. The test condition determining unit determines a test condition of a test to be conducted on the chips, based on a result of the estimation made by the withstand voltage estimating unit.

Test condition determining apparatus and test condition determining method

A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases. The carrier concentration of the carrier concentration transition layer has the concentration gradient that falls within a predetermined concentration range lying between a first concentration gradient condition and a second concentration gradient condition.

Semiconductor wafer, semiconductor device, and method for producing semiconductor device

A power converter includes: a base conductor, an electrically heating member which is provided on the base conductor, a noise reduction capacitor of flat plate-shape in which via an insulator, a plurality of first electrodes and second electrodes are alternately layered, on one surface, the first electrode in an outermost layer is exposed and on another surface, the second electrode in an outermost layer is exposed, a relay conductor which is electrically connected to other members from the electrically heating member via the noise reduction capacitor, and the second electrode in an outermost layer of the noise reduction capacitor is face-joined to a face of the base conductor at a side where the electrically heating member is provided and the first electrode in an outermost layer and the relay conductor are face-joined.

Power conversion device

A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E-4 [J] or higher is introduced into the growth furnace.

Manufacturing method and apparatus for manufacturing silicon carbide epitaxial wafer

The present invention relates to a laminated structure for realizing an arbitrary hollow structure by laminating in a predetermined order a plurality of plate-like members formed by punching in an arbitrary configuration. The plurality of plate-like members have a plurality of identification structure portions for individually identifying the plate-like members, and the plurality of identification structure portions are on the same side surface of a laminated structure thus obtained.

Laminated structure

A method for producing a phospholipid using transphosphatidylation, which comprises homogenizing a mixture of a raw material phospholipid, a hydroxyl-containing acceptor, phospholipase D, and water in the absence of an organic solvent to obtain a homogenized mixture; and subjecting the homogenized mixture to a transphosphatidylation reaction at 15&#xb0; C. to 65&#xb0; C. The homogenized mixture has a lamellar lyotropic liquid crystal structure. An objective phospholipid can be obtained from the homogenized mixture through transphosphatidylation without using an organic solvent or calcium.

Method for producing phosholipid

A cerebration improver having a prominent action for increasing brain glucose level has an effect of improving the cerebration of a subject administered with the improver. The cerebration improver contains as the effective ingredient phosphatidyl-L-serine, or lysophosphatidyl-L-serine produced by eliminating the fatty acid chain at the position .alpha. or .beta. of phosphatidyl-L-serine, or the salts thereof. The phosphatidyl-L-serine has a structural fatty acid chain derived from at least one raw material lecithin selected from the group consisting of soy bean lecithin, rapeseed lecithin or egg yolk lecithin. Using the raw material lecithin as the substrate, phosphatidyl-L-serine can be produced by utilizing transphosphatidylation.

Cerebration improver

Process for producing phosphatidylserines having long chain unsaturated

Thrombolytic peptide, production thereof, and thrombolytic agent

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Tokyo, Japan

Masashi Sakai